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general description the max16047/max16049 eeprom-configurable system managers monitor, sequence, and track multiple system voltages. the max16047 manages up to twelve system voltages simultaneously, and the max16049 manages up to eight supply voltages. these devices integrate an ana- log-to-digital converter (adc) for monitoring supply volt- ages, and configurable outputs for sequencing and tracking supplies (during power-up and power-down). nonvolatile eeprom registers are configurable for storing upper and lower voltage limits, setting timing and sequencing requirements, and for storing critical fault data for read back following failures. an internal 1% accurate 10-bit adc measures each input and compares the result to one upper, one lower, and one selectable upper or lower limit. a fault signal asserts when a monitored voltage falls outside the set limits. up to three independent fault output signals are configurable to assert under various fault conditions. the integrated sequencer/tracker allows precise control over the power-up and power-down order of up to twelve (max16047) or up to eight (max16049) power supplies. four channels (en_out1?n_out4) support closed- loop tracking using external series mosfets. six outputs (en_out1?n_out6) are configurable with charge- pump outputs to directly drive mosfets without closed- loop tracking. the max16047/max16049 include six programmable general-purpose inputs/outputs (gpios). in addition to serving as eeprom-configurable i/o pins, the gpios are also configurable as dedicated fault outputs, as a watchdog input or output (wdi/wdo), or as a manual reset ( mr ). the max16047/max16049 feature two methods of fault management for recording information during critical fault events. the fault logger records a failure in the internal eeprom and sets a lock bit protecting the stored fault data from accidental erasure. an i 2 c/smbus-compatible or a jtag serial interface configures the max16047/max16049. these devices are offered in a 56-pin 8mm x 8mm tqfn package and are fully specified from -40? to +85?. features operate from 3v to 14v 1% accurate 10-bit adc monitors 12/8 inputs 12/8 monitored inputs with one overvoltage/ one undervoltage/one selectable limit nonvolatile fault event logger power-up and power-down sequencing capability 12/8 outputs for sequencing/power-good indicators closed-loop tracking for up to four channels two programmable fault outputs and one reset output six general-purpose input/outputs configurable as: dedicated fault output watchdog timer function manual reset i 2 c/smbus-compatible and jtag interface eeprom-configurable time delays and thresholds 100 bytes of internal user eeprom 56-pin (8mm x 8mm) tqfn package -40? to +85? operating temperature range applications servers workstations storage systems networking/telecom max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ________________________________________________________________ maxim integrated products 1 ordering information part temp range pin-package max16047 etn+ -40? to +85? 56 tqfn-ep* max16049 etn+ -40? to +85? 56 tqfn-ep* 19-1869; rev 4; 9/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. selector guide and pin configurations appear at end of data sheet. evaluation kit available smbus is a trademark of intel corp.
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 2 _______________________________________________________________________________________ mon1 mon2?on11 mon12 v supply v cc v cc +3.3v gnd a0 c scl sda reset fault int reset int i/o wdi wdo en_out1 en_out2 en_out11 en_out12 en max16047a gnd out in dc-dc en gnd out in dc-dc en gnd out in dc-dc en 10 f dbp 1 f abp 1 f typical operating circuit max16047/max16049
max16047/max16049 absolute maximum ratings electrical characteristics (v cc = 3v to 14v, t a = -40? to +85?, unless otherwise specified. typical values are at v cc = 3.3v, t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ....................?0.3v to +15v en, mon_, scl, sda, a0 to gnd ...........................-0.3v to +6v gpio_, en_out7?n_out12, reset (configured as open drain) to gnd.......................-0.3v to +6v en_out1?n_out6 (configured as open-drain) to gnd ....................-0.3v to +12v gpio_, en_out, reset (configured as push-pull) to gnd .........-0.3v to (v dbp + 0.3v) dbp, abp to gnd ......-0.3v to the lower of 3v and (v cc + 0.3v) tck, tms, tdi to gnd..........................................-0.3v to +3.6v tdo to gnd .............................................-0.3v to (v dbp + 0.3v) en_out1?n_out6 (configured as charge pump) to gnd .-0.3v to (v mon1? + 6v) continuous current (all pins)............................................?0ma continuous power dissipation (t a = +70?) 56-pin tqfn (derate 47.6mw/? above +70?) .......3810mw* thermal resistance ja ................................21?/w jc ...............................0.6?/w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units reset output asserted low 1.4 operating voltage range v cc 314 v undervoltage lockout v uvlo (note 2) 2.85 v undervoltage-lockout hysteresis uvlo hys 50 mv supply current i cc v cc = 14v, v en = 3.3v, no load on any output 3.8 5 ma dbp regulator voltage v dbp c dbp = 1?, no load on any output 2.6 2.7 2.8 v abp regulator voltage v abp c abp = 1?, no load 2.78 2.88 2.96 v boot time t boot v cc > v uvlo 0.8 1.5 ms internal timing accuracy (note 3) -5 +5 % adc adc resolution 10 bits mon_ range set to ?0?in r0fh?11h 0.65 mon_ range set to ?0?in r0fh?11h 0.75 adc total unadjusted error (note 4) adc err mon_ range set to ?0?in r0fh?11h 0.95 %fsr adc integral nonlinearity adc inl 0.8 lsb adc differential nonlinearity adc dnl 0.8 lsb adc total monitoring cycle time t cycle all channels monitored, no mon_ fault detected (note 5) 80 100 ? mon1?on4 46.5 100 mon_ input impedance r in mon5?on12 65 140 k * as per jedec 51 standard, multilayer board (pcb). 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers _______________________________________________________________________________________ 3
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units mon_ range set to ?0?in r0fh?11h 5.6 mon_ range set to ?1?in r0fh?11h 2.8 adc mon_ ranges adc rng mon_ range set to ?0?in r0fh?11h 1.4 v mon_ range set to ?0?in r0fh?11h 5.46 mon_ range set to ?1?in r0fh?11h 2.73 adc lsb step size adc lsb mon_ range set to ?0?in r0fh?11h 1.36 mv v th_en_r en voltage rising 0.525 en input-voltage threshold v th_en_f en voltage falling 0.487 0.500 0.512 v en input current i en -0.5 +0.5 a en input voltage range 0 5.5 v closed-loop tracking tracking differential voltage stop ramp v trk v ins_ > v th_pl, v ins_ < v th_pg 150 mv tracking differential voltage hysteresis 20 %v trk tracking differential fault voltage v trk_f v ins_ > v th_pl , v ins_ < v th_pg 285 330 375 mv slew-rate register set to ?0 640 800 960 slew-rate register set to ?1 320 400 480 slew-rate register set to ?0 160 200 240 track/sequence slew-rate rising or falling trk slew slew-rate register set to ?1 80 100 120 v/s power-good register set to ?0, v mon_ = 3.5v 94 95 96 power-good register set to ?1, v mon_ = 3.5v 91.5 92.5 93.5 power-good register set to ?0, v mon_ = 3.5v 89 90 91 ins_ power-good threshold v th_pg power-good register set to ?1, v mon_ = 3.5v 86.5 87.5 88.5 %v m on_ power-good threshold hysteresis v pg_hys 0.5 %v th_pg power-low threshold v th_pl ins_ falling 125 142 160 mv power-low hysteresis v th_pl_hys 10 mv gpio_ input impedance gpio inr gpio_ configured as ins_ 75 100 145 k ins_ to gnd pulldown impedance when enabled ins rpd v ins_ = 2v 100 electrical characteristics (continued) (v cc = 3v to 14v, t a = -40? to +85?, unless otherwise specified. typical values are at v cc = 3.3v, t a = +25?.) (note 1)
max16047/max16049 electrical characteristics (continued) (v cc = 3v to 14v, t a = -40? to +85?, unless otherwise specified. typical values are at v cc = 3.3v, t a = +25?.) (note 1) parameter symbol conditions min typ max units outputs (en_out_, reset , gpio_) output-voltage low v ol i sink = 2ma 0.4 v output-voltage high (push-pull) i source = 100? 2.4 v 1 gpio1?pio4, v gpio_ = 3.3v 1 output leakage (open drain) i out_lkg gpio1?pio4, v gpio_ = 5v 22 ? en_out_ overdrive (charge pump) (en_out1 to en_out6 only) volts above v mon_ v ov i gate_ = 0.5? 4.6 5.1 5.6 v en_out_ pullup current (charge pump) i chg_up during power-up/power-down, v gate_ = 1v 4.5 6 a en_out_ pulldown current (charge pump) i chg_down during power-up/power-down, v gate_ = 5v 10 ? inputs (a0, gpio_) logic-input low voltage v il 0.8 v logic-input high voltage v ih 2.0 v smbus interface logic-input low voltage v il input voltage falling 0.8 v logic-input high voltage v ih input voltage rising 2.0 v v cc shorted to gnd, scl/sda at 0v or 3.3v -1 +1 input leakage current -1 +1 ? output-voltage low v ol i sink = 3ma 0.4 v input capacitance c in 5pf smbus timing serial clock frequency f scl 400 khz bus free time between stop t buf 1.3 ? start condition setup time t su:sta 0.6 ? start condition hold time t hd:sta 0.6 ? stop condition setup time t su:sto 0.6 ? clock low period t low 1.3 ? clock high period t high 0.6 ? data setup time t su:dat 200 ns output fall time t of 10pf c bus 400pf 250 ns receive 0 data hold time t hd:dat transmit 0.3 0.9 ? pulse width of spike suppressed t sp 30 ns 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers _______________________________________________________________________________________ 5
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 6 _______________________________________________________________________________________ electrical characteristics (continued) (v cc = 3v to 14v, t a = -40? to +85?, unless otherwise specified. typical values are at v cc = 3.3v, t a = +25?.) (note 1) parameter symbol conditions min typ max units jtag interface tdi, tms, tck logic-low input voltage v il input voltage falling 0.55 v tdi, tms, tck logic-high input voltage v ih input voltage rising 2 v tdo logic-output low voltage v ol_tdo v dbp 2.5v, i sink = 2ma 0.4 v tdo logic-output high voltage v oh_tdo v dbp 2.5v, i source = 200? 2.4 v tdo leakage current tdo high impedance -1 +1 ? tdi, tms pullup resistors r jpu pullup to v dbp 71013k input/output capacitance c i/o 5pf jtag timing tck clock period t 1 1000 ns tck high/low time t 2, t 3 50 500 ns tck to tms, tdi setup time t 4 15 ns tck to tms, tdi hold time t 5 15 ns tck to tdo delay t 6 500 ns tck to tdo high-z delay t 7 500 ns eeprom timing eeprom byte write cycle time t wr (note 6) 10.5 12 ms note 1: specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at t a = +25? and t a = +85?. specifications at t a = -40? are guaranteed by design. note 2: v uvlo is the minimum voltage on v cc to ensure the device is eeprom configured. note 3: applies to reset , fault, delay, and watchdog timeouts. note 4: total unadjusted error is a combination of gain, offset, and quantization error. note 5: guaranteed by design. note 6: an additional cycle is required when writing to configuration memory for the first time.
max16047/max16049 stop condition repeated start condition start condition t high t low t r t f t su:dat t su:sta t su:sto t hd:sta t buf t hd:sta t hd:dat scl sda start condition figure 1. i 2 c/smbus timing diagram tck t 1 t 2 t 3 t 4 t 5 t 6 t 7 tdi, tms tdo figure 2. jtag timing diagram 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers _______________________________________________________________________________________ 7
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 8 _______________________________________________________________________________________ v cc supply current vs. v cc supply voltage max16047 toc01 v cc (v) i cc (ma) 13 12 1 2 3 5 6 7 8 9 10 4 11 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 014 t a = +85 c t a = -40 c t a = +25 c normalized mon_ threshold vs. temperature max16047 toc02 temperature ( c) normalized mon_ threshold 75 60 30 45 -15 0 15 -30 0.992 0.994 0.996 0.998 1.000 1.002 1.004 1.006 1.008 1.010 0.990 -45 90 2.8v range, half scale, puv threshold normalized en threshold vs. temperature max16047 toc03 temperature ( c) normalized en threshold 75 60 30 45 -15 0 15 -30 0.975 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 1.025 1.030 0.970 -45 90 typical operating characteristics (v cc = 3.3v, t a = +25?, unless otherwise noted.) transient duration vs. threshold overdrive (en) max16047 toc04 en overdrive (mv) transient duration ( s) 10 20 40 60 80 100 120 140 160 0 1 100 normalized reset timeout period vs. temperature max16047 toc05 temperature ( c) normalized reset timeout 75 60 30 45 -15 0 15 -30 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 0.90 -45 90 mon_ puv threshold overdrive vs. transient duration max16047 toc06 threshold overdrive (mv) transient duration ( s) 835 670 175 340 505 20 40 60 80 100 120 140 160 0 10 1000 deglitch = 16 deglitch = 8 deglitch = 4 deglitch = 2 output-voltage low vs. sink current max16047 toc07 sink current (ma) output-voltage low (v) 5 4 1 2 3 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0 06 en_out_ gpio_
max16047/max16049 tracking mode with fast shutdown max16047 toc13 20ms/div 1v/div 0v ins4 ins3 ins2 ins1 sequencing mode max16047 toc14 40ms/div 1v/div 0v ins4 ins3 ins2 ins1 fet turn-on with charge pump max16047 toc11 20ms/div v en_out_ 10v/div v source 2v/div i drain 1a/div 0v 0v 0a tracking mode max16047 toc12 20ms/div 1v/div 0v ins4 ins3 ins2 ins1 output-voltage high vs. source current (charge-pump output) max16047 toc08 source current ( a) output-voltage high (v) 6 5 4 3 2 1 1 2 3 4 5 6 0 07 output-voltage high vs. source current (push-pull output) max16047 toc09 source current ( a) output-voltage high (v) 300 200 100 2.45 2.50 2.55 2.60 2.65 2.70 2.40 0 400 adc accuracy vs. temperature max16047 toc10 temperature ( c) total unadjusted error (%) 75 60 30 45 -15 0 15 -30 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 -45 90 typical operating characteristics (continued) (v cc = 3.3v, t a = +25?, unless otherwise noted.) 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers _______________________________________________________________________________________ 9
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 10 ______________________________________________________________________________________ adc inl max16047 toc17 input voltage (digital code) adc inl (lsb) 896 768 512 640 256 384 128 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 1024 internal timing accuracy vs. temperature max16047 toc18 temperature ( c) normalized slot delay 75 60 30 45 -15 0 15 -30 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 0.95 -45 90 mixed mode max16047 toc15 20ms/div 1v/div 0v ins4 ins3 ins2 ins1 adc dnl max16047 toc16 input voltage (digital code) adc dnl (lsb) 896 768 512 640 256 384 128 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 1024 typical operating characteristics (continued) (v cc = 3.3v, t a = +25?, unless otherwise noted.)
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 11 pin description pin max16047 max16049 name function 1? 1? mon1?on8 adc monitored voltage inputs. set adc input range for each mon_ through configuration registers. measured values are written to adc registers and can be read back through the i 2 c or jtag interface. 9?2 mon9?on12 adc monitored voltage inputs. set adc input range through configuration registers. measured values are written to adc registers and can be read back through the i 2 c or jtag interface. 13 13 reset configurable reset output 14 14 a0 four-state smbus address. address sampled upon por. connect a0 to ground, dbp, scl, or sda to program an individual address when connecting multiple devices. see the i 2 c/smbus-compatible serial interface section. 15 15 scl smbus serial clock input 16 16 sda smbus serial data open-drain input/output 17 17 tms jtag test mode select 18 18 tdi jtag test data in 19 19 tck jtag test clock 20 20 tdo jtag test data out 21, 40 21, 40 gnd ground. connect all gnd connections together. 22 22 gpio6 23 23 gpio5 general-purpose input/output. gpio6 and gpio5 are configurable as open-drain or push-pull outputs, dedicated fault outputs, or for watchdog functionality. gpio5 is configurable as a watchdog input (wdi). gpio6 is configurable as a watchdog output (wdo). gpio6 is also configurable for margining. use the eeprom to configure gpio5 and gpio6. see the general-purpose inputs/outputs section. 24 24 en analog enable input. apply a voltage greater than the 0.525v (typ) threshold to enable all outputs. the power-down sequence is triggered when en falls below 0.5v (typ) and all outputs are deasserted. 25?6 9?2, 25?6, 53?6 n.c. no connection. must be left unconnected.
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 12 ______________________________________________________________________________________ pin description (continued) pin max16047 max16049 name function 37 37 abp internal analog voltage bypass. bypass abp to gnd with a 1? ceramic capacitor. abp powers the internal circuitry of the max16047/max16049. do not use abp to power any external circuitry. 38 38 v cc power-supply input. bypass v cc to gnd with a 10? ceramic capacitor. 39 39 dbp internal digital voltage bypass. bypass dbp to gnd with a 1? ceramic capacitor. dbp supplies power to the eeprom memory, to the internal logic circuitry, and to the internal charge pumps when the programmable outputs are configured as charge pumps. all push-pull outputs are referenced to dbp. do not use dbp to power any external circuitry. 41 41 gpio1 general-purpose input/output 1. configure gpio1 as a logic input, a return sense line for closed-loop tracking, an open-drain/push-pull fault output, or an open-drain/push- pull output port. use the eeprom to configure gpio1. see the general-purpose inputs/outputs section. 42 42 gpio2 general-purpose input/output 2. gpio2 is configurable as a logic input, a return sense line for closed-loop tracking, an open-drain/push-pull fault output, or an open-drain/ push-pull output port. use the eeprom to configure gpio2. see the general-purpose inputs/outputs section. 43 43 gpio3 general-purpose input/output 3. gpio3 is configurable as a logic input, a return sense line for closed-loop tracking, an open-drain/push-pull fault output, or an open-drain/ push-pull output port. use the eeprom to configure gpio3. see the general-purpose inputs/outputs section. 44 44 gpio4 general-purpose input/output 4. gpio4 is configurable as a logic input, a return sense line for closed-loop tracking, an open-drain/push-pull fault output, or an open-drain/ push-pull output port. gpio4 is also configurable as an active-low manual reset, mr . use the eeprom to configure gpio4. see the general-purpose inputs/outputs section. 45?0 45?0 en_out1 en_out6 output. en_out1?n_out6 are configurable with active-high/active-low logic and with an open-drain or push-pull configuration. program the eeprom to configure en_out1?n_out6 as a charge-pump output 5v greater than the monitored input voltage (v mon_ + 5v). en_out1?n_out4 can also be used for closed-loop tracking. 51, 52 51, 52 en_out7 en_out8 output. configure en_out_ with active-low/active-high logic and with an open-drain or push-pull configuration. 53?6 en_out9 en_out12 output. configure en_out_ with active-low/active-high logic and with an open-drain or push-pull configuration. ep exposed pad. internally connected to gnd. connect to gnd. ep also functions as a heatsink to maximize thermal dissipation. do not use as the main ground connection.
max16047/max16049 functional diagram en v th_en voltage scaling and mux 10-bit adc (sar) ( ) max16049 only. adc registers threshold registers digital comparators ram registers eeprom registers logic sequencer closed-loop tracker i 2 c slave interface jtag interface mon1 mon12 (mon1 mon8) reset fault1 fault2 mr watchdog timer wdi gpio control wdo gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 ins1 ins2 ins3 ins4 en_out1 en_out12 (en_out1 en_out8) en_out1 en_out4 a0 sda scl tms tck tdi tdo margin faultpu gnd v cc nonvolatile fault event logger max16047 max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 13
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 14 ______________________________________________________________________________________ register summary (all registers 8-bits wide) note: this data sheet uses a specific convention for referring to bits within a particular address location. as an example, r0fh[3:0] refers to bit 3 through 0 in register with address 15 decimal. page register description adc conversion results (registers r00h to r17h) input adc conversion results. adc writes directly to these registers during normal operation. adc input ranges (mon1?on12) are selected with registers r0fh to r11h. failed line flags (registers r18h to r19h) voltage fault flag bits. flags for each input signal when undervoltage or overvoltage threshold is exceeded. extended gpio data (registers r1ah to r1bh) gpio state data. used to read back and control the state of each gpio. adc range selections (registers r0fh to r11h) adc input voltage range. selects the voltage range of the monitored inputs. fault behavior (registers r47h to r4ch) selects how the device should operate during faults. options include latch-off or autoretry after fault. the autoretry delay is selectable (r4fh). use registers r48h through r4ch to select fault conditions that trigger a critical fault event. gpio configuration (registers r1ch to r1eh) general-purpose input/output configuration registers. gpios are configurable as a manual-reset input, a margin disable input, a watchdog timer input and output, logic inputs/outputs, fault-dependent outputs, or as the feedback/pulldown inputs (ins_) for closed-loop tracking. overvoltage and undervoltage thresholds (registers r23h to r46h) input overvoltage and undervoltage thresholds. adc conversion results are compared to overvoltage and undervoltage threshold values stored here. mon_ voltages exceeding threshold values trigger a fault event. programmable output configuration (registers r1fh to r22h) programmable output configurations. selectable output configurations include: active- low or active-high, open-drain or push-pull outputs. en_out1?n_out6 are configurable as charge-pump outputs and en_out1?n_out4 can be configured for closed-loop tracking. reset and fault outputs (registers r15h to r1bh) reset , fault1 , and fault2 output configuration. programs the functionality of the reset , fault1 , and fault2 outputs, as well as which inputs they depend on. sequencing-mode configuration (registers r50h to r5bh and r5eh to r63h) assign inputs and outputs for sequencing. select sequence delays (20? to 1.6s) with registers r50h through r54h. use register r54h to enable/disable the reverse sequence bit for power-down operation. software enable and margin (register r4dh) use register r4dh to set the software enable bit, to select early warning thresholds and undervoltage/overvoltage, to enable/disable margining, and to enable/disable the watchdog for independent/dependent mode. default and eeprom watchdog functionality (register r55h) configure watchdog functionality for gpio5 and gpio6. fault log results (registers r00h to r0eh) adc conversion results and failed-line flags at the time of a fault. these values are recorded by the fault event logger at the time of a critical fault. eeprom user eeprom (registers r9ch to rffh) user-available eeprom
max16047/max16049 detailed description getting started the max16047 is capable of managing up to twelve system voltages simultaneously, and the max16049 can manage up to eight system voltages. after boot- up, if en is high and the software enable bit is set to ?,?an internal multiplexer cycles through each input. at each multiplexer stop, the 10-bit adc converts the monitored analog voltage to a digital result and stores the result in a register. each time the multiplexer finish- es a conversion (8.3? max), internal logic circuitry compares the conversion results to the overvoltage and undervoltage thresholds stored in memory. if a conver- sion violates a programmed threshold, the conversion can be configured to generate a fault. logic outputs can be programmed to depend on many combinations of faults. additionally, faults are programmable to trig- ger the nonvolatile fault logger, which writes all fault information automatically to the eeprom and write-pro- tects the data to prevent accidental erasure. the max16047/max16049 contain both i 2 c/smbus- compatible and jtag serial interfaces for accessing reg- isters and eeprom. use only one interface at any given time. for more information on how to access the internal memory through these interfaces, see the i 2 c/smbus- compatible serial interface and jtag serial interface sections. registers are divided into three pages with access controlled by special i 2 c and jtag commands. the factory-default values at por (power-on reset) for all ram registers are ??. por occurs when v cc reach- es the undervoltage-lockout threshold (uvlo) of 2.85v (max). at por, the device begins a boot-up sequence. during the boot-up sequence, all monitored inputs are masked from initiating faults and eeprom contents are copied to the respective register locations. during boot- up, the max16047/max16049 are not accessible through the serial interface. the boot-up sequence can take up to 1.5ms, after which the device is ready for normal operation. reset is low during boot-up and asserts after boot-up for its programmed timeout period once all monitored channels are within their respective thresholds. during boot-up, the gpios and en_outs are high impedance. accessing the eeprom the max16047/max16049 memory is divided into three separate pages. the default page, selected by default at por, contains configuration bits for all func- tions of the part. the extended page contains the adc conversion results and gpio input and output regis- ters. finally, the eeprom page contains all stored con- figuration information as well as saved fault data and user-defined data. see the register map table for more information on the function of each register. during the boot-up sequence, the contents of the eeprom (r0fh to r7dh) are copied into the default page (r0fh to r7dh). registers r00h to r0eh of the eep- rom page contain saved fault data. the jtag and i 2 c interfaces provide access to all three pages. each interface provides commands to select and deselect a particular page: 98h(i 2 c)/09h(jtag)?witches to the extended page. switch back to the default page with 99h(i 2 c)/0ah(jtag). 9ah(i 2 c)/0bh(jtag)?witches to the eeprom page. switch back to the default page with 9bh(i 2 c)/0ch(jtag). see the i 2 c/smbus-compatible serial interface or the jtag serial interface section. power apply 3v to 14v to v cc to power the max16047/ max16049. bypass v cc to ground with a 10? capacitor. two internal voltage regulators, abp and dbp, supply power to the analog and digital circuitry within the device. do not use abp or dbp to power external circuitry. abp is a 2.85v (typ) voltage regulator that powers the internal analog circuitry. bypass the abp output to gnd with a 1? ceramic capacitor installed as close to the device as possible. dbp is an internal 2.7v (typ) voltage regulator. eeprom and digital circuitry are powered by dbp. all push-pull outputs are referenced to dbp. dbp supplies the input voltage to the internal charge pumps when the program- mable outputs are configured as charge-pump outputs. bypass the dbp output to gnd with a 1? ceramic capacitor installed as close as possible to the device. 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 15
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 16 ______________________________________________________________________________________ enable to initiate sequencing/tracking and enable monitoring, the voltage at en must be above 0.525v and the software enable bit in r4dh[0] must be set to ?.?to power down and disable monitoring, either pull en below 0.5v or set the software enable bit to ?.?see table 1 for the software enable bit configurations. connect en to abp if not used. if a fault condition occurs during the power-up cycle, the en_out_ outputs are powered down immediately, independent of the state of en. if operating in latch-on fault mode, toggle en or toggle the software enable bit to clear the latch condition and restart the device once the fault condition has been removed. table 1. eeprom software enable configurations register/ eeprom address bit range description 0 software enable bit 0 = enabled. en must also be high to begin sequencing 1 = disabled (factory default) 1 margin bit 1 = margin functionality is enabled 0 = margin disabled 2 early warning selection bit 0 = early warning thresholds are undervoltage thresholds 1 = early warning thresholds are overvoltage thresholds 3 watchdog mode selection bit 0 = watchdog timer is in dependent mode 1 = watchdog timer is in independent mode 4dh [7:4] not used voltage monitoring the max16047/max16049 feature an internal 10-bit adc that monitors the mon_ voltage inputs. an internal multiplexer cycles through each of the twelve inputs, taking 100? (typ) for a complete monitoring cycle. each acquisition takes approximately 8.3?. at each multiplexer stop, the 10-bit adc converts the analog input to a digital result and stores the result in a regis- ter. adc conversion results are stored in registers r00h to r17h in the extended page. use the i 2 c or jtag seri- al interface to read adc conversion results. see the i 2 c/smbus-compatible serial interface or the jtag serial interface section for more information on access- ing the extended page. the max16047 provides twelve inputs, mon1?on12, for voltage monitoring. the max16049 provides eight inputs, mon1?on8, for voltage monitoring. each input voltage range is programmable in registers r0fh to r11h (see table 2). when mon_ configuration registers are set to ?1,?mon_ voltages are not moni- tored or converted, and the multiplexer does not stop at these inputs, decreasing the total cycle time. these inputs cannot be configured to trigger fault conditions. the three programmable thresholds for each monitored voltage include an overvoltage, an undervoltage, and an early warning threshold that can be set in r4dh[2] to be either an undervoltage or overvoltage threshold. see the faults section for more information on setting over- voltage and undervoltage thresholds. all voltage thresholds are 8 bits wide. the 8 msbs of the 10-bit adc conversion result are compared to these overvolt- age and undervoltage thresholds. for any undervoltage or overvoltage condition to be monitored and any faults detected, the mon_ input must be assigned to a particular sequence order. see the sequencing section for more details on assigning mon_ inputs.
max16047/max16049 table 2. input monitor ranges and enables register/ eeprom address bit range description [1:0] mon1 voltage range selection: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon1 is not converted or monitored [3:2] mon2 voltage range selection: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon2 is not converted or monitored [5:4] mon3 voltage range selection: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon3 is not converted or monitored 0fh [7:6] mon4 voltage range selection: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon4 is not converted or monitored [1:0] mon5 voltage range selection: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon5 is not converted or monitored [3:2] mon6 voltage range selection: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon6 is not converted or monitored [5:4] mon7 voltage range selection: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon7 is not converted or monitored 10h [7:6] mon8 voltage range selection: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon8 is not converted or monitored 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 17
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 18 ______________________________________________________________________________________ table 2. input monitor ranges and enables (continued) register/ eeprom address bit range description [1:0] mon9 voltage range selection*: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon9 is not converted or monitored [3:2] mon10 voltage range selection*: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon10 is not converted or monitored [5:4] mon11 voltage range selection*: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon11 is not converted or monitored 11h [7:6] mon12 voltage range selection*: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon12 is not converted or monitored * max16047 only
max16047/max16049 the extended memory page contains the adc conver- sion result registers (see table 3). these registers are also used internally for fault threshold comparison. voltage-monitoring thresholds are compared with the 8 msbs of the conversion results. inputs that are not enabled are not converted by the adc; they contain the last value acquired before that channel was disabled. the adc conversion result registers are reset to 00h at boot-up. these registers are not reset when a reboot command is executed. table 3. adc conversion registers extended page address bit range description 00h [7:0] mon1 adc conversion result (msb) [7:6] mon1 adc conversion result (lsb) 01h [5:0] reserved 02h [7:0] mon2 adc conversion result (msb) [7:6] mon2 adc conversion result (lsb) 03h [5:0] reserved 04h [7:0] mon3 adc conversion result (msb) [7:6] mon3 adc conversion result (lsb) 05h [5:0] reserved 06h [7:0] mon4 adc conversion result (msb) [7:6] mon4 adc conversion result (lsb) 07h [5:0] reserved 08h [7:0] mon5 adc conversion result (msb) [7:6] mon5 adc conversion result (lsb) 09h [5:0] reserved 0ah [7:0] mon6 adc conversion result (msb) [7:6] mon6 adc conversion result (lsb) 0bh [5:0] reserved 0ch [7:0] mon7 adc conversion result (msb) [7:6] mon7 adc conversion result (lsb) 0dh [5:0] reserved 0eh [7:0] mon8 adc conversion result (msb) [7:6] mon8 adc conversion result (lsb) 0fh [5:0] reserved 10h [7:0] mon9 adc conversion result (msb)* [7:6] mon9 adc conversion result (lsb)* 11h [5:0] reserved 12h [7:0] mon10 adc conversion result (msb)* [7:6] mon10 adc conversion result (lsb)* 13h [5:0] reserved 14h [7:0] mon11 adc conversion result (msb)* [7:6] mon11 adc conversion result (lsb)* 15h [5:0] reserved 16h [7:0] mon12 adc conversion result (msb)* [7:6] mon12 adc conversion result (lsb)* 17h [5:0] reserved * max16047 only 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 19
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 20 ______________________________________________________________________________________ general-purpose inputs/outputs gpio1?pio6 are programmable general-purpose inputs/outputs. gpio1?pio6 are configurable as a manual reset input, a margin disable input, a watchdog timer input and output, logic inputs/outputs, fault- dependent outputs, or as the feedback inputs (ins_) for closed-loop tracking. when programmed as out- puts, gpios are open drain or push-pull. see registers r1ch to r1eh in tables 4 and 5 for more detailed infor- mation on configuring gpio1?pio6. table 4. general-purpose io configuration registers register/ eeprom address bit range description [2:0] gpio1 configuration register [5:3] gpio2 configuration register 1ch [7:6] gpio3 configuration register (lsb) [0] gpio3 configuration register (msb) [3:1] gpio4 configuration register [6:4] gpio5 configuration register 1dh [7] gpio6 configuration register (lsb) [1:0] gpio6 configuration register (msb) 1eh [7:2] reserved table 5. gpio mode selection configuration bits gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 000 ins1 ins2 ins3 ins4 margin input 001 push-pull logic input/output push-pull logic input/output push-pull logic input/output push-pull logic input/output push-pull logic input/output push-pull logic input/output 010 open-drain logic input/output open-drain logic input/output open-drain logic input/ output open-drain logic input/output open-drain logic input/ output open-drain logic input/ output 011 push-pull any_fault output push-pull any_fault output push-pull any_fault output push-pull any_fault output push-pull fault1 output push-pull fault2 output 100 open-drain any_fault output open-drain any_fault output open-drain any_fault output open-drain any_fault output open-drain fault1 output open-drain fault2 output 101 logic input logic input logic input logic input logic input logic input 110 open-drain wdo output 111 mr input wdi input open-drain faultpu output note: the dash ?represents a reserved gpio configuration. do not set any gpio to these values.
max16047/max16049 voltage tracking sense (ins_) inputs gpio1?pio4 are configurable as feedback sense return inputs (ins_) for closed-loop tracking. connect the gate of an external n-channel mosfet to each en_out_ configured for closed-loop tracking. connect ins_ inputs to the source of the mosfets for tracking feedback. internal comparators monitor ins_ with respect to a control tracking ramp voltage for power-up/power- down and control each en_out_ voltage. under nor- mal conditions each ins_ voltage tracks the ramp voltage until the power-good voltage threshold has been reached. the slew rate for the ramp voltage and the ins_ to mon_ power-good threshold are program- mable. see the closed-loop tracking section. ins_ connections also act as 100 pulldowns for closed-loop tracking channels or for other power sup- plies, if ins_ are connected to the outputs of the sup- plies. set the appropriate bits in r4eh[7:4] to enable pulldown functionality. see table 12. general-purpose logic inputs/outputs configure gpio1?pio6 to be used as general-pur- pose inputs/outputs. write values to gpios through r1ah when operating as outputs, and read values from r1bh when operating as inputs. register r1bh is read- only. see table 6 for more information on reading and writing to the gpios as logic inputs/outputs. both regis- ters r1ah and r1bh are located in the extended page and are therefore not loaded from eeprom on boot-up. table 6. gpio data-in/data-out data extended page address bit range description [0] gpio logic output data 0 = gpio1 is a logic-low output 1 = gpio1 is a logic-high output [1] 0 = gpio2 is a logic-low output 1 = gpio2 is a logic-high output [2] 0 = gpio3 is a logic-low output 1 = gpio3 is a logic-high output [3] 0 = gpio4 is a logic-low output 1 = gpio4 is a logic-high output [4] 0 = gpio5 is a logic-low output 1 = gpio5 is a logic-high output [5] 0 = gpio6 is a logic-low output 1 = gpio6 is a logic-high output 1ah [7:6] not used [0] gpio logic input data gpio1 logic-input state [1] gpio2 logic-input state [2] gpio3 logic-input state [3] gpio4 logic-input state [4] gpio5 logic-input state [5] gpio6 logic-input state 1bh [7:6] not used 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 21
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 22 ______________________________________________________________________________________ any_fault outputs gpio1?pio4 are configurable as active-low push-pull or open-drain fault-dependent outputs. these outputs assert when any monitored input exceeds an overvolt- age, undervoltage, or early warning threshold. fault1 and fault2 gpio5 and gpio6 are configurable as dedicated fault outputs, fault1 and fault2 , respectively. fault outputs can assert on one or more overvoltage, under- voltage, or early warning conditions for selected inputs. fault1 and fault2 dependencies are set using reg- isters r15h to r18h. see table 7. if a fault output depends on more than one mon_, the fault output will assert if one or more mon_ exceeds a programmed threshold voltage. table 7. fault1 and fault2 output configuration and dependencies register/ eeprom address bit range description [0] 1 = fault1 is a digital output dependent on mon1 [1] 1 = fault1 is a digital output dependent on mon2 [2] 1 = fault1 is a digital output dependent on mon3 [3] 1 = fault1 is a digital output dependent on mon4 [4] 1 = fault1 is a digital output dependent on mon5 [5] 1 = fault1 is a digital output dependent on mon6 [6] 1 = fault1 is a digital output dependent on mon7 15h [7] 1 = fault1 is a digital output dependent on mon8 [0] 1 = fault1 is a digital output dependent on mon9* [1] 1 = fault1 is a digital output dependent on mon10* [2] 1 = fault1 is a digital output dependent on mon11* [3] 1 = fault1 is a digital output dependent on mon12* [4] 1 = fault1 is a digital output that depends on the overvoltage thresholds at the input selected by r15h and r16h[3:0] [5] 1 = fault1 is a digital output that depends on the undervoltage thresholds at the input selected by r15h and r16h[3:0] [6] 1 = fault1 is a digital output that depends on the early warning thresholds at the input selected by r15h and r16h[3:0] 16h [7] 0 = fault1 is an active-low digital output 1 = fault1 is an active-high digital output [0] 1 = fault2 is a digital output dependent on mon1 [1] 1 = fault2 is a digital output dependent on mon2 [2] 1 = fault2 is a digital output dependent on mon3 [3] 1 = fault2 is a digital output dependent on mon4 [4] 1 = fault2 is a digital output dependent on mon5 [5] 1 = fault2 is a digital output dependent on mon6 [6] 1 = fault2 is a digital output dependent on mon7 17h [7] 1 = fault2 is a digital output dependent on mon8
max16047/max16049 fault-on power-up ( faultpu ) gpio6 indicates a fault during power-up or power- down when configured as a ?ault-on power-up?output. under these conditions, all en_out_ voltages are pulled low and fault data is saved to nonvolatile eeprom. see the faults section. margin gpio6 is configurable as an active-low margin input. drive margin low before varying system voltages above or below the thresholds to avoid signaling an error. drive margin high for normal operation. when margin is pulled low or r4dh[1] is a ?,?the mar- gin function is enabled. fault1 , fault2 , any_fault, and reset are latched in their current state. threshold violations will be ignored, and faults will not be logged. manual reset ( mr ) gpio4 is configurable to act as an active-low manual reset input, mr . drive mr low to assert reset . reset remains low for the selected reset timeout period after mr transitions from low to high. see the reset section for more information on selecting a reset timeout period. watchdog input (wdi) and output (wdo) set r1eh[1:0] and r1dh[7] to ?10?to configure gpio6 as wdo. set r1dh[6:4] to ?11?to configure gpio5 as wdi. wdo is an open-drain active-low output. see the watchdog timer section for more information about the operation of the watchdog timer. programmable outputs (en_out1?n_out12) the max16047 includes twelve programmable outputs, and the max16049 includes eight programmable out- puts. these outputs are capable of connecting to either the enable (en) inputs of a dc-dc or ldo power supply or to the gates of series-pass mosfets for closed-loop tracking mode, or for charge-pump mode. selectable output configurations include: active-low or active-high, open-drain or push-pull. en_out1?n_out4 are also configurable for closed-loop tracking, and en_out1 en_out6 can act as charge-pump outputs with no closed-loop tracking. use the registers r1fh to r22h to configure outputs. see table 8 for detailed information on configuring en_out1?n_out12. table 7. fault1 and fault2 output configuration and dependencies (continued) register/ eeprom address bit range description [0] 1 = fault2 is a digital output dependent on mon9* [1] 1 = fault2 is a digital output dependent on mon10* [2] 1 = fault2 is a digital output dependent on mon11* [3] 1 = fault2 is a digital output dependent on mon12* [4] 1 = fault2 is a digital output that depends on the overvoltage thresholds at the input selected by r17h and r18h[3:0] [5] 1 = fault2 is a digital output that depends on the undervoltage thresholds at the input selected by r17h and 18h[3:0] [6] 1 = fault2 is a digital output that depends on the early warning thresholds at the input selected by r17h and r18h[3:0] 18h [7] 0 = fault2 is an active-low digital output 1 = fault2 is an active-high digital output * max16047 only 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 23
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 24 ______________________________________________________________________________________ table 8. en_out1?n_out12 configuration register/ eeprom address bit range description [2:0] en_out1 configuration: 000 = en_out1 is an open-drain active-low output 001 = en_out1 is an open-drain active-high output 010 = en_out1 is a push-pull active-low output 011 = en_out1 is a push-pull active-high output 100 = en_out1 is used in closed-loop tracking 101 = en_out1 is configured with a charge-pump output (mon1 + 5v) capable of driving an external n-channel mosfet 110 = reserved 111 = reserved [5:3] en_out2 configuration: 000 = en_out2 is an open-drain active-low output 001 = en_out2 is an open-drain active-high output 010 = en_out2 is a push-pull active-low output 011 = en_out2 is a push-pull active-high output 100 = en_out2 is used in closed-loop tracking 101 = en_out2 is configured with a charge-pump output (mon2 + 5v) capable of driving an external n-channel mosfet 110 = reserved 111 = reserved 1fh [7:6] en_out3 configuration (lsbs): 000 = en_out3 is an open-drain active-low output 001 = en_out3 is an open-drain active-high output 010 = en_out3 is a push-pull active-low output 011 = en_out3 is a push-pull active-high output 100 = en_out3 is used in closed-loop tracking 101 = en_out3 is configured with a charge-pump output (mon3 + 5v) capable of driving an external n-channel mosfet 110 = reserved 111 = reserved
max16047/max16049 table 8. en_out1?n_out12 configuration (continued) register/ eeprom address bit range description [0] en_out3 configuration (msb) ?ee r1fh[7:6] [3:1] en_out4 configuration: 000 = en_out4 is an open-drain active-low output 001 = en_out4 is an open-drain active-high output 010 = en_out4 is a push-pull active-low output 011 = en_out4 is a push-pull active-high output 100 = en_out4 is used in closed-loop tracking 101 = en_out4 is configured with a charge-pump output (mon4 + 5v) capable of driving an external n-channel mosfet 110 = reserved 111 = reserved [6:4] en_out5 configuration: 000 = en_out5 is an open-drain active-low output 001 = en_out5 is an open-drain active-high output 010 = en_out5 is a push-pull active low output 011 = en_out5 is a push-pull active-high output 100 = reserved. en_out5 is not usable for closed-loop tracking. 101 = en_out5 is configured with a charge-pump output (mon5 + 5v) capable of driving an external n-channel mosfet 110 = reserved 111 = reserved 20h [7] en_out6 configuration (lsb) ?ee r21h[1:0] [1:0] en_out6 configuration (msbs): 000 = en_out6 is an open-drain active-low output 001 = en_out6 is an open-drain active-high output 010 = en_out6 is a push-pull active-low output 011 = en_out6 is a push-pull active-high output 100 = reserved. en_out6 is not useable for closed-loop tracking. 101 = en_out6 is configured with a charge-pump output (mon6 + 5v) capable of driving an external n-channel mosfet 110 = reserved 111 = reserved [3:2] en_out7 configuration: 00 = en_out7 is an open-drain active-low output 01 = en_out7 is an open-drain active-high output 10 = en_out7 is a push-pull active-low output 11 = en_out7 is a push-pull active-high output [5:4] en_out8 configuration: 00 = en_out8 is an open-drain active-low output 01 = en_out8 is an open-drain active-high output 10 = en_out8 is a push-pull active-low output 11 = en_out8 is a push-pull active-high output 21h [7:6] en_out9 configuration*: 00 = en_out9 is an open-drain active-low output 01 = en_out9 is an open-drain active-high output 10 = en_out9 is a push-pull active-low output 11 = en_out9 is a push-pull active-high output 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 25
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 26 ______________________________________________________________________________________ table 8. en_out1?n_out12 configuration (continued) register/ eeprom address bit range description [1:0] en_out10 configuration*: 00 = en_out10 is an open-drain active-low output 01 = en_out10 is an open-drain active-high output 10 = en_out10 is a push-pull active-low output 11 = en_out10 is a push-pull active-high output [3:2] en_out11 configuration*: 00 = en_out11 is an open-drain active-low output 01 = en_out11 is an open-drain active-high output 10 = en_out11 is a push-pull active-low output 11 = en_out11 is a push-pull active-high output [5:4] en_out12 configuration*: 00 = en_out12 is an open-drain active-low output 01 = en_out12 is an open-drain active high output 10 = en_out12 is a push-pull active-low output 11 = en_out12 is a push-pull active-high output 22h [7:6] reserved * max16047 only charge-pump configuration en_out1?n_out6 can act as high-voltage charge- pump outputs to drive up to six external n-channel mosfets. during sequencing, an en_out_ output configured this way drives 6? until the voltage reach- es 5v above the corresponding mon_ to fully enhance the external n-channel mosfet. for example, en_out2 will rise to 5v above mon2. see the sequencing section for more detailed information on power-supply sequencing. closed-loop tracking operation en_out1?n_out4 can operate in closed-loop track- ing mode. when configured for closed-loop tracking, en_out1?n_out4 are capable of driving the gates of up to four external n-channel mosfets. for closed- loop tracking, configure gpio1?pio4 as return-sense line inputs (ins_) to be used in conjunction with en_out1?n_out4 and mon1?on4. see the closed-loop tracking section. open-drain output configuration connect an external pullup resistor from the output to an external voltage up to 6v (abs max, en_out7 en_out12) or 12v (abs max, en_out1?n_out6) when configured as an open-drain output. choose the pullup resistor depending on the number of devices connected to the open-drain output and the allowable current consumption. the open-drain output configura- tion allows wire-ored connection. push-pull output configuration the max16047/max16049s?programmable outputs sink 2ma and source 100? when configured as push- pull outputs. en_out_ state during power-up when v cc is ramped from 0v to the operating supply voltage, the en_out_ output is high impedance until v cc is approximately 2.4v and then en_out_ will be in its configured deasserted state. see figures 3 and 4. reset is configured as an active-low open-drain out- put pulled up to v cc through a 10k resistor for figures 3 and 4.
max16047/max16049 max16047 fig03 20ms/div v cc 2v/div en_out_ 2v/div 0v reset 2v/div 0v 0v figure 3. reset and en_out_ during power-up, en_out_ is in open-drain active-low configuration max16047 fig04 10ms/div v cc 2v/div en_out_ 2v/div 0v reset 2v/div 0v 0v high-z asserted low uvlo figure 4. reset and en_out_ during power-up, en_out_ is in push-pull active-high configuration sequencing each en_out_ has one or more associated mon_ inputs, facilitating the voltage monitoring of multiple power supplies. to sequence a system of power sup- plies safely, the output voltage of a power supply must be good before the next power supply may turn on. connect en_out_ outputs to the enable input of an external power supply and connect mon_ inputs to the output of the power supply for voltage monitoring. more than one mon_ may be used if the power supply has multiple outputs. sequence order the max16047/max16049 utilize a system of ordered slots to sequence multiple power supplies. to deter- mine the sequence order, assign each en_out_ to a slot ranging from slot 0 to slot 11. en_out_(s) assigned to slot 0 are turned on first, followed by out- puts assigned to slot 1, and so on through slot 11. multiple en_out_s assigned to the same slot turn on at the same time. each slot has a built-in configurable sequence delay (registers r50h to r54h) ranging from 20? to 1.6s. during a reverse sequence, slots are turned off in reverse order starting from slot 11. the max16047/max16049 may be configured to power-down in simultaneous mode or in reverse sequence mode as set in r54h[4]. see tables 9, 10, and 11 for the en_out_ slot assignment bits, and tables 12 and 13 for the sequence delays. monitoring inputs while sequencing an enabled mon_ input may be assigned to a slot rang- ing from slot 1 to slot 12. monitoring inputs are always checked at the beginning of a slot. the inputs are given the power-up fault delay within which they must satisfy the programmed undervoltage limit; otherwise a fault condition will occur. the fault occurs regardless of the critical fault enable bits. this undervoltage limit cannot be disabled during power-up and power-down. en_out_s configured for open-drain, push-pull, or charge-pump operation are always asserted at the end of a slot, following the sequence delay. see tables 9, 10, and 11 for the mon_ slot assignment bits. slot 0 does not monitor any mon_ input. instead, slot 0 waits for the software enable bit r4dh[0] to be a logic ? and for the voltage on en to rise above 0.525v before asserting any assigned outputs. outputs assigned to slot 0 are asserted before the slot 0 sequence delay. generally, slot 0 controls the enable inputs of power supplies that are first in the sequence. similarly, slot 12 does not control any en_out_ out- puts. rather, slot 12 monitors assigned mon_ inputs and then enters the power-on state. generally, slot 12 monitors the last power supplies in the sequence. the power-up sequence is complete when any mon_ inputs assigned to slot 12 exceed their undervoltage thresh- olds and the sequence delay is expired. if no mon_ inputs are assigned to slot 12, the power-up sequence is complete after the slot sequence delay is expired. the output rail(s) of a power supply should be moni- tored by one or more mon_ inputs placed in the suc- ceeding slot, ensuring that the output of the supply is not checked until it has first been turned on. for exam- ple, if a power supply uses en_out1 located in slot 3 and has two monitoring inputs, mon1 and mon2, they must both be assigned to slot 4. in this example, en_out1 turns on at the end of slot 3. at the start of slot 4, mon1 and mon2 must exceed the undervolt- age threshold before the programmed power-up fault delay; otherwise a fault triggers. 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 27
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 28 ______________________________________________________________________________________ table 9. mon_ and en_out_ slot assignment registers register/ eeprom address bit range description [3:0] mon1 slot assignment register 56h [7:4] mon2 slot assignment register [3:0] mon3 slot assignment register 57h [7:4] mon4 slot assignment register [3:0] mon5 slot assignment register 58h [7:4] mon6 slot assignment register [3:0] mon7 slot assignment register 59h [7:4] mon8 slot assignment register [3:0] mon9 slot assignment register* 5ah [7:4] mon10 slot assignment register* [3:0] mon11 slot assignment register* 5bh [7:4] mon12 slot assignment register* [3:0] en_out1 slot assignment register 5eh [7:4] en_out2 slot assignment register [3:0] en_out3 slot assignment register 5fh [7:4] en_out4 slot assignment register [3:0] en_out5 slot assignment register 60h [7:4] en_out6 slot assignment register [3:0] en_out7 slot assignment register 61h [7:4] en_out8 slot assignment register [3:0] en_out9 slot assignment register* 62h [7:4] en_out10 slot assignment register* [3:0] en_out11 slot assignment register* 63h [7:4] en_out12 slot assignment register * * max16047 only reset deassertion after any mon_ inputs assigned to slot 12 exceed their undervoltage thresholds, the reset timeout begins. when the reset timeout completes, reset deasserts. the reset timeout period is set in r19h[6:4]. see table 21. power-down power-down starts when en is pulled low or the software enable bit is set to ?.? reset asserts as soon as power-down begins regardless of the reset output dependencies. power down en_out_s simultaneously or in reverse sequence mode by setting the reverse sequence bit (r54h[4]) appropriately. in reverse sequence mode (r54h[4] set to ??, the en_out_s assigned to slot 11 deassert, the max16047/max16049 wait for the slot 11 sequence delay and then proceed to slot 10, and so on until the en_out_s assigned to slot 0 turn off. when simultaneous power-down is selected (r54h[4] set to ??, all en_out_s turn off at the same time.
max16047/max16049 table 10. mon_ slot assignment configuration bits description 0000 mon_ is not assigned to a slot 0001 mon_ is assigned to slot 1 0010 mon_ is assigned to slot 2 0011 mon_ is assigned to slot 3 0100 mon_ is assigned to slot 4 0101 mon_ is assigned to slot 5 0110 mon_ is assigned to slot 6 0111 mon_ is assigned to slot 7 1000 mon_ is assigned to slot 8 1001 mon_ is assigned to slot 9 1010 mon_ is assigned to slot 10 1011 mon_ is assigned to slot 11 1100 mon_ is assigned to slot 12 1101 not used 1110 not used 1111 not used table 11. en_out_ slot assignment configuration bits description 0000 en_out_ is not assigned to a slot 0001 en_out_ is assigned to slot 0 0010 en_out_ is assigned to slot 1 0011 en_out_ is assigned to slot 2 0100 en_out_ is assigned to slot 3 0101 en_out_ is assigned to slot 4 0110 en_out_ is assigned to slot 5 0111 en_out_ is assigned to slot 6 1000 en_out_ is assigned to slot 7 1001 en_out_ is assigned to slot 8 1010 en_out_ is assigned to slot 9 1011 en_out_ is assigned to slot 10 1100 en_out_ is assigned to slot 11 1101 not used 1110 not used 1111 not used 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 29
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 30 ______________________________________________________________________________________ table 12. sequence delays and fault recovery register/ eeprom address bit range description [1:0] power-up fault timeout 00 = 25ms 01 = 50ms 10 = 100ms 11 = 200ms [3:2] power-down fault timeout 00 = 25ms 01 = 50ms 10 = 100ms 11 = 200ms [4] ins1 pulldown resistor enable 0 = pulldown resistor for ins1 is disabled 1 = pulldown resistor for ins1 is enabled [5] ins2 pulldown resistor enable 0 = pulldown resistor for ins2 is disabled 1 = pulldown resistor for ins2 is enabled [6] ins3 pulldown resistor enable 0 = pulldown resistor for ins3 is disabled 1 = pulldown resistor for ins3 is enabled 4eh [7] ins4 pulldown resistor enable 0 = pulldown resistor for ins4 is disabled 1 = pulldown resistor for ins4 is enabled [2:0] autoretry timeout 000 = 20? 001 = 12.5ms 010 = 25ms 011 = 50ms 100 = 100ms 101 = 200ms 110 = 400ms 111 = 1.6s [3] fault recovery mode 0 = autoretry procedure is performed following a fault event 1 = latch-off on fault [5:4] slew rate 00 = 800v/s 01 = 400v/s 10 = 200v/s 11 = 100v/s 4fh [7:6] fault deglitch 00 = 2 conversions 01 = 4 conversions 10 = 8 conversions 11 = 16 conversions
max16047/max16049 table 12. sequence delays and fault recovery (continued) register/ eeprom address bit range description [2:0] slot 0 sequence delay [5:3] slot 1 sequence delay 50h [7:6] slot 2 sequence delay (lsbs) [0] slot 2 sequence delay (msb)?ee r50h[7:6] [3:1] slot 3 sequence delay [6:4] slot 4 sequence delay 51h [7] slot 5 sequence delay (lsb)?ee r52h[1:0] [1:0] slot 5 sequence delay [4:2] slot 6 sequence delay 52h [7:5] slot 7 sequence delay [2:0] slot 8 sequence delay [5:3] slot 9 sequence delay 53h [7:6] slot 10 sequence delay (lsbs) [0] slot 10 sequence delay (msb)?ee r53h[7:6] [3:1] slot 11 sequence delay [4] reverse sequence 0 = power down all en_out_s at the same time (simultaneously) 1 = controlled power-down will be reverse of power-up sequence 54h [7:5] not used table 13. slot sequence delay selection configuration bits slot sequence delay 000 20? 001 12.5ms 010 25ms 011 50ms 100 100ms 101 200ms 110 400ms 111 1.6s 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 31
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 32 ______________________________________________________________________________________ closed-loop tracking the max16047/max16049 track up to four voltages during any time slot except slot 0 and slot 12. configure gpio1?pio4 as sense line inputs (ins_) to monitor tracking voltages. configure gpio6 as faultpu to indicate tracking faults, if desired. see the general-purpose inputs/outputs section for information on configuring gpios. for closed-loop tracking, use mon1, en_out1, and ins1 together to form a complete channel. use mon2, en_out2, and ins2 to form a second complete chan- nel. use mon3, en_out3, and ins3 together to form a third channel; and use mon4, en_out4, and ins4 to form a fourth channel. when configured for closed-loop tracking, assign each en_out_ to the same slot as its associated single monitoring input (mon_). for example, if en_out2 is assigned to slot 3, the monitoring input is mon2 and must be assigned to slot 3. this is because the mon_ input, checked at the start of the slot, must be valid before tracking can begin. tracking begins immediate- ly and must finish before the power-up fault timeout expires, or a fault will trigger. en_out_ configured for closed-loop tracking cannot be assigned to slot 0. the tracking control circuitry includes a ramp generator and a comparator control block for each tracked volt- age (see the functional diagram and figure 5). the comparator control block compares each ins_ voltage with a control voltage ramp. if ins_ voltages vary from the control ramp by more than 150mv (typ), the com- parator control block signals an alert that dynamically stops the ramp until the slow ins_ voltage rises to with- in the allowed voltage window. the total tracking time is extended under these conditions, but must still com- plete within the selected power-up/power-down fault timeout. the power-up/power-down tracking fault time- out period is adjustable through r4eh[3:0]. a voltage difference between any two tracking ins_ voltages exceeding 330mv generates a tracking fault, forcing all en_out_ voltages low and generating a fault log. if configured as faultpu , gpio6 asserts when a tracking fault occurs. the comparator control blocks also monitor ins_ volt- ages with respect to input (mon_) voltages. under nor- mal conditions each ins_ tracks the control ramp until the ins_ voltages reach the configured power-good (pg) thresholds, set as a programmable percentage of the mon_ voltage. use register r64h to set the pg thresholds (table 14). once pg is detected, the exter- nal n-channel fet saturates with 5v (typ) applied between gate and source. the slew rate for the control ramp is programmable from 100v/s to 800v/s in r4fh[5:4] (see table 12). power-down initiates when en is forced low or when the software enable bit in r4dh[0] is set to ?.?if the reverse sequence bit is set (r54h[4]) ins_ voltages fol- low a falling reference ramp to ground as long as mon_ voltages remain high enough to supply the required voltage/current. if a monitored voltage drops faster than the control ramp voltage or the correspond- ing mon_ voltage falls too quickly, power-down track- ing operation is terminated and all en_out_ voltages are immediately forced to ground. if the reverse sequence bit is set to ?,?all en_out_ voltages are forced low simultaneously. mon_ en_out_ ins_ v in v out reference ramp logic adc mux v th_pg 100 gate drive figure 5. closed-loop tracking
max16047/max16049 table 14. power-good (pg) thresholds register/ eeprom address bit range description [1:0] 00 = pg is asserted when monitored v mon1 is 95% of v ins1 01 = pg is asserted when monitored v mon1 is 92.5% of v ins1 10 = pg is asserted when monitored v mon1 is 90% of v ins1 11 = pg is asserted when monitored v mon1 is 87.5% of v ins1 [3:2] 00 = pg is asserted when monitored v mon2 is 95% of v ins2 01 = pg is asserted when monitored v mon2 is 92.5% of v ins2 10 = pg is asserted when monitored v mon2 is 90% of v ins2 11 = pg is asserted when monitored v mon2 is 87.5% of v ins2 [5:4] 00 = pg is asserted when monitored v mon3 is 95% of v ins3 01 = pg is asserted when monitored v mon3 is 92.5% of v ins3 10 = pg is asserted when monitored v mon3 is 90% of v ins3 11 = pg is asserted when monitored v mon3 is 87.5% of v ins3 64h [7:6] 00 = pg is asserted when monitored v mon4 is 95% of v ins4 01 = pg is asserted when monitored v mon4 is 92.5% of v ins4 10 = pg is asserted when monitored v mon4 is 90% of v ins4 11 = pg is asserted when monitored v mon4 is 87.5% of v ins4 the max16047/max16049 include selectable internal 100 pulldown resistors to ensure that tracked voltages are not held high by large external capacitors during a fault event. the pulldowns help to ensure that monitored ins_ voltages are fully discharged before the next power-up cycle is initiated. these pulldowns are high impedance during normal operation. set r4eh[7:4] to ? to enable the pulldown resistors ( table 12). these pull- down resistors may also be used with en_out1 en_out4 channels not configured for closed-loop track- ing, which is useful to discharge the output capacitors of a dc-dc converter during shutdown. for this case, con- figure the gpio as an ins_ input and set the 100 pull- down bit, but do not enable closed-loop tracking. connect the ins_ input to the output of the power supply. 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 33
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 34 ______________________________________________________________________________________ faults the max16047/max16049 monitor the input (mon_) channels and compare the results with an overvoltage threshold, an undervoltage threshold, and a selectable overvoltage or undervoltage early warning threshold. based on these conditions, the max16047/max16049 can assert various fault outputs and save specific infor- mation about the channel conditions and voltages into the nonvolatile eeprom. once a critical fault event occurs, the failing channel condition, adc conversions at the time of the fault, or both may be saved by config- uring the event logger. the event logger records a sin- gle failure in the internal eeprom and sets a lock bit which protects the stored fault data from accidental erasure on a subsequent power-up. the max16047/max16049 are capable of measuring overvoltage and undervoltage fault events. fault condi- tions are detected at the end of each adc conversion. an overvoltage event occurs when the voltage at a monitored input exceeds the overvoltage threshold for that input. an undervoltage fault occurs when the volt- age at a monitored input falls below the undervoltage threshold. fault thresholds are set in registers r23h to r46h as shown in table 15. disabled inputs are not monitored for fault conditions and are skipped over by the input multiplexer. only the upper 8 bits of a conver- sion result are compared with the programmed fault thresholds. inputs not assigned to a sequencing slot are not monitored for fault conditions but are still recorded in the adc results registers. the general-purpose inputs/outputs (gpio1?pio6) can be configured as any_fault outputs or dedicated fault1 and fault2 outputs to indicate fault condi- tions. these fault outputs are not masked by the critical fault enable bits shown in table 17. see the general- purpose inputs/outputs section for more information on configuring gpios as fault outputs. table 15. fault thresholds register/ eeprom address description 23h mon1 early warning threshold 24h mon1 overvoltage threshold 25h mon1 undervoltage threshold 26h mon2 early warning threshold 27h mon2 overvoltage threshold 28h mon2 undervoltage threshold 29h mon3 early warning threshold 2ah mon3 overvoltage threshold 2bh mon3 undervoltage threshold 2ch mon4 early warning threshold 2dh mon4 overvoltage threshold 2eh mon4 undervoltage threshold 2fh mon5 early warning threshold 30h mon5 overvoltage threshold 31h mon5 undervoltage threshold 32h mon6 early warning threshold 33h mon6 overvoltage threshold 34h mon6 undervoltage threshold register/ eeprom address description 35h mon7 early warning threshold 36h mon7 overvoltage threshold 37h mon7 undervoltage threshold 38h mon8 early warning threshold 39h mon8 overvoltage threshold 3ah mon8 undervoltage threshold 3bh mon9 early warning threshold* 3ch mon9 overvoltage threshold* 3dh mon9 undervoltage threshold* 3eh mon10 early warning threshold* 3fh mon10 overvoltage threshold* 40h mon10 undervoltage threshold* 41h mon11 early warning threshold* 42h mon11 overvoltage threshold* 43h mon11 undervoltage threshold* 44h mon12 early warning threshold* 45h mon12 overvoltage threshold* 46h mon12 undervoltage threshold* * max16047 only
max16047/max16049 deglitch fault conditions are detected at the end of each con- version. if the voltage on an input falls outside a moni- tored threshold for one acquisition, the input multiplexer remains on that channel and performs several succes- sive conversions. to trigger a fault, the input must stay outside the threshold for a certain number of acquisi- tions as determined by the deglitch setting in r4fh[7:6] (see table 19). fault flags fault flags indicate the fault status of a particular input. the fault flag of any monitored input in the device can be read at any time from registers r18h and r19h in the extended page, as shown in table 16. clear a fault flag by writing a ??to the appropriate bit in the flag register. unlike the fault signals sent to the fault outputs, these bits are masked by the critical fault enable bits (see table 17). the fault flag will only be set if the matching enable bit in the critical fault enable register is also set. critical faults if a specific input threshold is critical to the operation of the system, an automatic fault log can be configured to shut down all the en_out_s and trigger a transfer of fault information to eeprom. for a fault condition to trigger a critical fault, set the appropriate enable bit in registers r48h to r4ch (see table 17). logged fault information is stored in eeprom registers r00h to r0eh (see table 18). once a fault log event occurs, the eeprom is locked and must be unlocked to enable a new fault log to be stored. write a ??to r5dh[1] to unlock the eeprom. fault information can be configured to store adc conversion results and/or fault flags in registers r01h and r02h. select the critical fault configuration in r47h[1:0]. set r47h[1:0] to ?1?to turn off the fault logger. all stored adc results are 8 bits wide. * max16047 only table 16. fault flags extended page address bit range description [0] 1 = mon1 conversion exceeds overvoltage or undervoltage thresholds [1] 1 = mon2 conversion exceeds overvoltage or undervoltage thresholds [2] 1 = mon3 conversion exceeds overvoltage or undervoltage thresholds [3] 1 = mon4 conversion exceeds overvoltage or undervoltage thresholds [4] 1 = mon5 conversion exceeds overvoltage or undervoltage thresholds [5] 1 = mon6 conversion exceeds overvoltage or undervoltage thresholds [6] 1 = mon7 conversion exceeds overvoltage or undervoltage thresholds 18h [7] 1 = mon8 conversion exceeds overvoltage or undervoltage thresholds [0] 1 = mon9 conversion exceeds overvoltage or undervoltage thresholds* [1] 1 = mon10 conversion exceeds overvoltage or undervoltage thresholds* [2] 1 = mon11 conversion exceeds overvoltage or undervoltage thresholds* [3] 1 = mon12 conversion exceeds overvoltage or undervoltage thresholds* 19h [7:4] not used 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 35
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 36 ______________________________________________________________________________________ table 17. critical fault configuration and enable bits register/ eeprom address bit range description [1:0] critical fault log control 00 = failed lines and adc conversion values save to eeprom upon critical fault 01 = failed line flags only saved to eeprom upon critical fault 10 = adc conversion values only saved to eeprom upon critical fault 11 = no information saved upon critical fault 47h [7:2] not used [0] 1 = fault log triggered when mon1 is below its undervoltage threshold [1] 1 = fault log triggered when mon2 is below its undervoltage threshold [2] 1 = fault log triggered when mon3 is below its undervoltage threshold [3] 1 = fault log triggered when mon4 is below its undervoltage threshold [4] 1 = fault log triggered when mon5 is below its undervoltage threshold [5] 1 = fault log triggered when mon6 is below its undervoltage threshold [6] 1 = fault log triggered when mon6 is below its undervoltage threshold 48h [7] 1 = fault log triggered when mon8 is below its undervoltage threshold [0] 1 = fault log triggered when mon9 is below its undervoltage threshold* [1] 1 = fault log triggered when mon10 is below its undervoltage threshold* [2] 1 = fault log triggered when mon11 is below its undervoltage threshold* [3] 1 = fault log triggered when mon12 is below its undervoltage threshold* [4] 1 = fault log triggered when mon1 is above its overvoltage threshold [5] 1 = fault log triggered when mon2 is above its overvoltage threshold [6] 1 = fault log triggered when mon3 is above its overvoltage threshold 49h [7] 1 = fault log triggered when mon3 is above its overvoltage threshold [0] 1 = fault log triggered when mon5 is above its overvoltage threshold [1] 1 = fault log triggered when mon6 is above its overvoltage threshold [2] 1 = fault log triggered when mon7 is above its overvoltage threshold [3] 1 = fault log triggered when mon8 is above its overvoltage threshold [4] 1 = fault log triggered when mon9 is above its overvoltage threshold* [5] 1 = fault log triggered when mon10 is above its overvoltage threshold* [6] 1 = fault log triggered when mon11 is above its overvoltage threshold* 4ah [7] 1 = fault log triggered when mon12 is above its overvoltage threshold* [0] 1 = fault log triggered when mon1 is above/below its early earning threshold [1] 1 = fault log triggered when mon2 is above/below its early warning threshold [2] 1 = fault log triggered when mon3 is above/below its early warning threshold [3] 1 = fault log triggered when mon4 is above/below its early warning threshold [4] 1 = fault log triggered when mon5 is above/below its early warning threshold [5] 1 = fault log triggered when mon6 is above/below its early warning threshold [6] 1 = fault log triggered when mon7 is above/below its early warning threshold 4bh [7] 1 = fault log triggered when mon8 is above/below its early warning threshold
max16047/max16049 * max16047 only table 17. critical fault configuration and enable bits (continued) register/ eeprom address bit range description [0] 1 = fault log triggered when mon9 is above/below its early warning threshold* [1] 1 = fault log triggered when mon10 is above/below its early warning threshold* [2] 1 = fault log triggered when mon11 is above/below its early warning threshold* [3] 1 = fault log triggered when mon12 is above/below its early warning threshold* 4ch [7:4] not used * max16047 only table 18. fault log eeprom eeprom address bit range description [3:0] power-up/power-down fault register slot where power-up/power-down fault is detected [4] tracking fault bits if ?,?tracking fault occurred on mon1/en_out1/ins1 [5] if ?,?tracking fault occurred on mon2/en_out2/ins2 [6] if ?,?tracking fault occurred on mon3/en_out3/ins3 00h [7] if ?,?tracking fault occurred on mon4/en_out4/ins4 [0] if ?,?fault occurred on mon1 [1] if ?,?fault occurred on mon2 [2] if ?,?fault occurred on mon3 [3] if ?,?fault occurred on mon4 [4] if ?,?fault occurred on mon5 [5] if ?,?fault occurred on mon6 [6] if ?,?fault occurred on mon7 01h [7] if ?,?fault occurred on mon8 [0] if ?,?fault occurred on mon9* [1] if ?,?fault occurred on mon10* [2] if ?,?fault occurred on mon11* [3] if ?,?fault occurred on mon12* 02h [7:4] not used 03h [7:0] mon_ adc fault information (only the 8 msbs of converted channels are saved following a fault event) mon1 conversion result at the time the fault log was triggered 04h [7:0] mon2 conversion result at the time the fault log was triggered 05h [7:0] mon3 conversion result at the time the fault log was triggered 06h [7:0] mon4 conversion result at the time the fault log was triggered 07h [7:0] mon5 conversion result at the time the fault log was triggered 08h [7:0] mon6 conversion result at the time the fault log was triggered 09h [7:0] mon7 conversion result at the time the fault log was triggered 0ah [7:0] mon8 conversion result at the time the fault log was triggered 0bh [7:0] mon9 conversion result at the time the fault log was triggered* 0ch [7:0] mon10 conversion result at the time the fault log was triggered* 0dh [7:0] mon11 conversion result at the time the fault log was triggered* 0eh [7:0] mon12 conversion result at the time the fault log was triggered* 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 37
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 38 ______________________________________________________________________________________ power-up/power-down faults all en_outs are deasserted if an overvoltage or under- voltage fault is detected during power-up/power-down (regardless of the critical fault enable bits). under these conditions, information of the failing slot is stored in eeprom r00h[3:0] unless the fault register is config- ured not to store any information by setting r47h[1:0] to ?1?(see table 17). if there is a tracking fault on a channel configured for closed-loop tracking, a fault log operation occurs and the bits representing the failed tracking channels are set to ??unless the fault register is configured not to store any information by setting r47h[1:0] to ?1?(see table 17). autoretry/latch mode for critical faults, the max16047/max16049 can be configured for one of two fault management methods: autoretry or latch-on-fault. set r4fh[3] to ??to select autoretry mode. in this configuration, the device will shut down after a critical fault event then restart follow- ing a configurable delay. use r4fh[2:0] to select an autoretry delay from 20? to 1.6s. see table 19 for more information on setting the autoretry delay. set r4fh[3] to ??to select the latch-on-fault mode. in this configuration en_out_s are deasserted after a critical fault event. the device does not re-initiate the power-up sequence until en is toggled or the software enable bit is reset to ?.?see the enable section for more information on setting the software enable bit. if fault information is stored in eeprom (see the critical faults section) and autoretry mode is selected, set an autoretry delay greater than the time required for the storing operation. if fault information is stored in eep- rom and latch-on-fault mode is chosen, toggle en or reset the software enable bit only after the completion of the storing operation. if saving information about the failed lines only, ensure a delay of at least 60ms before the restart procedure. otherwise, ensure a minimum 204ms timeout. this ensures that adc conversions are completed and values are stored correctly in eeprom. see table 20 for more information about required fault log operation periods. table 19. fault recovery configuration register/ eeprom address bit range description [2:0] autoretry delay 000 = 20? 001 = 12.5ms 010 = 25ms 011 = 50ms 100 = 100ms 101 = 200ms 110 = 400ms 111 = 1.6s [3] fault recovery mode 0 = autoretry procedure is performed following a fault event 1 = latchoff on fault [5:4] slew rate 00 = 800v/s 01 = 400v/s 10 = 200v/s 11 = 100v/s 4fh [7:6] fault deglitch 00 = 2 conversions 01 = 4 conversions 10 = 8 conversions 11 = 16 conversions
max16047/max16049 reset the reset output, reset , is asserted during power- up/power-down and deasserts following the reset time- out period once the power-up sequence is complete. the power-up sequence is complete when any mon_ inputs assigned to slot 12 exceed their undervoltage thresholds. if no mon_ inputs are assigned to slot 12, the power-up sequence is complete after the slot sequence delay is expired. reset is a configurable output that monitors selected mon_ voltages during normal operation. reset also depends on any monitoring input that has one or more critical fault enable bits set. use r19h[1:0] to configure reset to assert on an overvoltage fault, undervoltage fault, or both. use r19h[3:2] to configure reset as an active-high/active-low push-pull/open-drain output. if desired, configure gpio4 as a manual reset input, mr , and pull mr low to assert reset . reset includes a programmable timeout. see table 21 for reset depen- dencies and configuration registers. table 20. eeprom fault log operation period fault control register r47h[1:0] description minimum required shutdown period (ms) 00 failed lines and adc values saved 204 01 failed lines saved 60 10 adc values saved 168 11 no information saved n/a table 21. reset configuration and dependencies register/ eeprom address bit range description [1:0] reset output configuration 00 = reset is asserted if at least one of the selected inputs exceeds its undervoltage threshold 01 = reset is asserted if at least one of the selected inputs exceeds its early warning threshold 10 = reset is asserted if at least one of the selected inputs exceeds its overvoltage threshold 11 = reset is asserted if any of the selected inputs exceeds undervoltage or overvoltage thresholds [2] 0 = reset is an active-low output 1 = reset is an active-high output [3] 0 = reset is a open-drain output 1 = reset is an push-pull output [6:4] reset timeout 000 = 25? 001 = 2ms 010 = 25ms 011 = 100ms 100 = 200ms 101 = 400ms 110 = 800ms 111 = 1600ms 19h [7] reserved 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 39
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 40 ______________________________________________________________________________________ watchdog timer the watchdog timer can operate together with or inde- pendently of the max16047/max16049. when operat- ing in dependent mode, the watchdog is not activated until the sequencing is complete and reset is de- asserted. when operating in independent mode, the watchdog timer is independent of the sequencing oper- ation and activates immediately after v cc exceeds the uvlo threshold and the boot phase is complete. set r4dh[3] to ??to configure the watchdog in dependent mode. set r4dh[3] to ??to configure the watchdog in independent mode. see table 22 for more information on configuring the watchdog timer in dependent or independent mode. dependent watchdog timer operation the watchdog timer can be used to monitor ? activity in two modes. flexible timeout architecture provides an adjustable watchdog startup delay of up to 128s, allow- ing complicated systems to complete lengthy boot-up routines. an adjustable watchdog timeout allows the supervisor to provide quick alerts when processor activity fails. after each reset event (v cc drops below uvlo then returns above uvlo, software reboot, man- ual reset ( mr ), en input going low then high, or watch- dog reset) and once sequencing is complete, the watchdog startup delay provides an extended time for the system to power up and fully initialize all ? and system components before assuming responsibility for routine watchdog updates. set r55h[6] to ??to enable the watchdog startup delay. set r55h[6] to ??to disable the watchdog startup delay. the normal watchdog timeout period, t wdi , begins after the first transition on wdi before the conclusion of the long startup watchdog period, t wdi_startup (figures 6 and 7). during the normal operating mode, wdo asserts if the ? does not toggle wdi with a valid transi- tion (high-to-low or low-to-high) within the standard timeout period, t wdi . wdo remains asserted until wdi is toggled or reset is asserted (figure 7). while en is low, or r55h[7] is a ?,?the watchdog timer is in reset. the watchdog timer does not begin counting until the power-on mode is reached and reset is deasserted. the watchdog timer is reset and wdo deasserts any time reset is asserted (figure 8). the watchdog timer will be held in reset while reset is asserted. the watchdog can be configured to control the reset output as well as the wdo output. reset is pulsed low for the reset timeout, t rp , when the watchdog timer expires and the watchdog reset output enable bit (r55h[7]) is set to ?.?therefore, wdo pulses low for a short time (approximately 1?) when the watchdog timer expires. reset is not affected by the watchdog timer when the reset output enable bit (r55h[7]) is set to ?. see table 23 for more information on configuring watchdog functionality. * max16047 only table 21 . reset configuration and dependencies (continued) register/ eeprom address bit range description [0] reset dependencies 1 = reset is dependent on mon1 [1] 1 = reset is dependent on mon2 [2] 1 = reset is dependent on mon3 [3] 1 = reset is dependent on mon4 [4] 1 = reset is dependent on mon5 [5] 1 = reset is dependent on mon6 [6] 1 = reset is dependent on mon7 1ah [7] 1 = reset is dependent on mon8 [0] 1 = reset is dependent on mon9* [1] 1 = reset is dependent on mon10* [2] 1 = reset is dependent on mon11* [3] 1 = reset is dependent on mon12* 1bh [7:4] reserved
max16047/max16049 last mon_ wdi v th t wdi_startup < t wdi t rp reset < t wdi figure 6. normal watchdog startup sequence wdi wdo 0v v cc 0v v cc < t wdi < t wdi < t wdi < t wdi > t wdi < t wdi < t wdi t wdi figure 7. watchdog timer operation wdi wdo 0v 0v v cc v cc 0v v cc < t wdi 1 s reset < t wdi < t wdi < t wdi t wdi t rp < t wdi_startup figure 8. watchdog startup sequence with watchdog reset enable bit (r55h[7]) set to ? 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 41
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 42 ______________________________________________________________________________________ table 22. watchdog mode selection register/ eeprom address bit range description 0 software enable bit 0 = enabled. en must also be high to begin sequencing. 1 = disabled (factory default) 1 margin bit 1 = margin functionality is enabled 0 = margin disabled 2 early warning selection bit 0 = early warning thresholds are undervoltage thresholds 1 = early warning thresholds are overvoltage thresholds 3 watchdog mode selection bit 0 = watchdog timer is in dependent mode 1 = watchdog timer is in independent mode 4dh [7:4] not used table 23. watchdog enables and configuration register/ eeprom address bit range description [2:0] watchdog timeout 000 = 1ms 001 = 4ms 010 = 12.5ms 011 = 50ms 100 = 200ms 101 = 800ms 110 = 1.6s 111 = 3.2s [4:3] watchdog startup delay 00 = 25.6s 01 = 51.2s 10 = 102.4s 11 = 128s [5] watchdog enable 1 = watchdog enabled 0 = watchdog disabled [6] watchdog startup delay enable 1 = watchdog startup delay enabled 0 = watchdog startup delay disabled 55h [7] watchdog reset output enable 1 = watchdog timeout asserts reset output 0 = watchdog timeout does not assert reset output
max16047/max16049 independent watchdog timer operation when r4dh[3] is ?,?the watchdog timer operates in the independent mode. in the independent mode, the watchdog timer operates as if it were a separate chip. the watchdog timer is activated immediately upon v cc exceeding uvlo and once the boot-up sequence is finished. if reset is asserted by the sequencer state machine, the watchdog timer and wdo will not be affected. there will be a long startup delay if r55h[6] is a ?.?if r55h[6] is a ?,?there will not be a long startup delay. in independent mode, if the watchdog reset output enable bit r55h[7] is set to ?,?when the watchdog timer expires, wdo will be asserted then reset will be asserted. wdo will then be deasserted. wdo will be low for 3 system clock cycles or approximately 1?. if the watchdog reset output enable bit (r55h[7]) is set to ?,?when the wdt expires, wdo will be asserted but reset will not be affected. miscellaneous table 24 lists several miscellaneous programmable items. register r5ch provides storage space for a user- defined configuration or firmware version number. bit r5dh[0] locks and unlocks the configuration registers. bit r5dh[1] locks and unlocks eeprom addresses 00h to 11h. the r65h[2:0] bits contain a read-only manufac- turing revision code. write data to eeprom r5dh as normally done; howev- er, to toggle a bit in register r5dh, write a ??to that bit. table 24. miscellaneous settings register/ eeprom address bit range description 5ch [7:0] user identification. 8 bits of memory for user-defined identification [0] configuration lock 0 = configuration registers and eeprom writable 1 = configuration registers and eeprom [except r5dh] locked [1] eeprom fault data lock flag (set automatically after fault log is triggered): 0 = eeprom is not locked. a triggered fault log stores fault information to eeprom. 1 = eeprom addresses 00h to 11h are locked. write a ??to this bit to toggle the flag. 5dh [7:2] not used [2:0] manufacturing revision code. this register is read only. not stored in eeprom. 65h [7:3] not used 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 43
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 44 ______________________________________________________________________________________ i 2 c/smbus-compatible serial interface the max16047/max16049 feature an i 2 c/smbus-com- patible 2-wire serial interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl facilitate bidirectional communication between the max16047/max16049 and the master device at clock rates up to 400khz. figure 1 shows the 2-wire interface timing diagram. the max16047/max16049 are trans- mit/receive slave-only devices, relying upon a master device to generate a clock signal. the master device (typically a ?) initiates a data transfer on the bus and generates scl to permit that transfer. a master device communicates to the max16047/ max16049 by transmitting the proper address followed by command and/or data words. the slave address input, a0, is capable of detecting four different states, allowing multiple identical devices to share the same seri- al bus. the slave address is described further in the slave address section. each transmit sequence is framed by a start (s) or repeated start (sr) condition and a stop (p) condition. each word transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse. scl is a logic input, while sda is an open-drain input/output. scl and sda both require external pullup resistors to generate the logic-high voltage. use 4.7k for most applications. bit transfer each clock pulse transfers one data bit. the data on sda must remain stable while scl is high (figure 9); otherwise the max16047/max16049 registers a start or stop condition (figure 10) from the master. sda and scl idle high when the bus is not busy. start and stop conditions both scl and sda idle high when the bus is not busy. a master device signals the beginning of a transmis- sion with a start condition by transitioning sda from high to low while scl is high. the master device issues a stop condition by transitioning sda from low to high while scl is high. a stop condition frees the bus for another transmission. the bus remains active if a repeated start condition is generated, such as in the block read protocol (see figure 1). early stop conditions the max16047/max16049 recognize a stop condition at any point during transmission except if a stop condi- tion occurs in the same high pulse as a start condition. this condition is not a legal i 2 c format; at least one clock pulse must separate any start and stop condition. repeated start conditions a repeated start may be sent instead of a stop condition to maintain control of the bus during a read operation. the start and repeated start condi- tions are functionally identical. data line stable, data valid sda scl change of data allowed figure 9. bit transfer p s start condition sda scl stop condition figure 10. start and stop conditions
max16047/max16049 acknowledge the acknowledge bit (ack) is the 9th bit attached to any 8-bit data word. the receiving device always gen- erates an ack. the max16047/max16049 generate an ack when receiving an address or data by pulling sda low during the 9th clock period (figure 11). when transmitting data, such as when the master device reads data back from the max16047/max16049, the device waits for the master device to generate an ack. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if the receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. the max16047/max16049 generate a nack after the command byte is received during a software reboot, while writing to the eeprom, or when receiving an illegal memory address. slave address use the slave address input, a0, to allow multiple identi- cal devices to share the same serial bus. connect a0 to gnd, dbp (or an external supply voltage greater than 2v), scl, or sda to set the device address on the bus. see table 25 for a listing of all possible 7-bit addresses. table 25. setting the i 2 c/smbus slave address a0 slave address 0 1010 00xr 1 1010 01xr scl 1010 10xr sda 1010 11xr x = don? care, r = read/write select bit. scl 1 s 2 89 sda by transmitter sda by receiver clock pulse for acknowledge nack ack figure 11. acknowledge 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 45
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 46 ______________________________________________________________________________________ send byte the send byte protocol allows the master device to send one byte of data to the slave device (see figure 12). the send byte presets a register pointer address for a subsequent read or write. the slave sends a nack instead of an ack if the master tries to send a memory address or command code that is not allowed. if the master sends 94h or 95h, the data is ack, because this could be the start of the write block or read block. if the master sends a stop condition before the slave asserts on ack, the internal address pointer does not change. if the master sends 96h, this signifies a software reboot. the send byte procedure is the following: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends an 8-bit memory address or com- mand code. 5) the addressed slave asserts an ack (or nack) on sda. 6) the master sends a stop condition. receive byte the receive byte protocol allows the master device to read the register content of the max16047/max16049 (see figure 12). the eeprom or register address must be preset with a send byte or write word protocol first. once the read is complete, the internal pointer increas- es by one. repeating the receive byte protocol reads the contents of the next address. the receive byte pro- cedure follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a read bit (high). 3) the addressed slave asserts an ack on sda. 4) the slave sends 8 data bits. 5) the master asserts a nack on sda. 6) the master generates a stop condition. write byte the write byte protocol (see figure 12) allows the mas- ter device to write a single byte in the default page, extended page, or eeprom page, depending on which page is currently selected. the write byte proce- dure is the following: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends an 8-bit memory address. 5) the addressed slave asserts an ack on sda. 6) the master sends an 8-bit data byte. 7) the addressed slave asserts an ack on sda. 8) the master sends a stop condition. to write a single byte, only the 8-bit memory address and a single 8-bit data byte are sent. the data byte is written to the addressed location if the memory address is valid. the slave will assert a nack at step 5 if the memory address is not valid. read byte the read byte protocol (see figure 12) allows the mas- ter device to read a single byte located in the default page, extended page, or eeprom page depending on which page is currently selected. the read byte proce- dure is the following: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends an 8-bit memory address. 5) the addressed slave asserts an ack on sda. 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave address and a read bit (high). 8) the addressed slave asserts an ack on sda. 9) the slave sends an 8-bit data byte. 10) the master asserts a nack on sda. 11) the master sends a stop condition. if the memory address is not valid, it is nacked by the slave at step 5 and the address pointer is not modified.
max16047/max16049 command codes the max16047/max16049 use eight command codes for block read, block write, and other commands. see table 26 for a list of command codes. to initiate a software reboot, send 96h using the send byte format. a software-initiated reboot is functionally the same as a hardware-initiated power-on reset. during boot-up, eeprom configuration data in the range of 0fh to 7dh is copied to the same register addresses in the default page. send command code 97h to trigger a fault store to eeprom. configure the critical fault log control register (r47h) to store adc conversion results and/or fault flags in registers once the command code has been sent. using command code 98h allows access to the extend- ed page, which contains registers for adc conversion results, and gpio input/output data. use command code 99h to return to the default page. send command code 9ah to access the eeprom page. once command code 9ah has been sent, all addresses are recognized as eeprom addresses only. send command code 9bh to return to the default page. block write the block write protocol (see figure 12) allows the master device to write a block of data (1 byte to 16 bytes) to memory. the destination address should be preloaded by a previous send byte command; other- wise the block write command begins to write at the current address pointer. after the last byte is written, the address pointer remains preset to the next valid address. if the number of bytes to be written causes the address pointer to exceed ffh for eeprom or 7dh for configuration registers, the address pointer stays at ffh or 7dh, overwriting this memory address with the remaining bytes of data. the last data byte sent is stored at register address ffh. the slave generates a nack at step 5 if the command code is invalid or if the device is busy, and the address pointer is not altered. the block write procedure is the following: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends the 8-bit command code for block write (94h). 5) the addressed slave asserts an ack on sda. 6) the master sends the 8-bit byte count (1 byte to 16 bytes), n . 7) the addressed slave asserts an ack on sda. 8) the master sends 8 bits of data. 9) the addressed slave asserts an ack on sda. 10) repeat steps 8 and 9 n - 1 times. 11) the master sends a stop condition. block read the block read protocol (see figure 12) allows the master device to read a block of up to 16 bytes from memory. read fewer than 16 bytes of data by issuing an early stop condition from the master, or by gener- ating a nack with the master. the destination address should be preloaded by a previous send byte com- mand; otherwise the block read command begins to read at the current address pointer. if the number of bytes to be read causes the address pointer to exceed ffh for the configuration register or eeprom, the address pointer stays at ffh and the last data byte read is from register rffh. the block read procedure is the following: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends 8 bits of the block read com- mand (95h). 5) the slave asserts an ack on sda, unless busy. 6) the master generates a repeated start condition. 7) the master sends the 7-bit slave address and a read bit (high). table 26. command codes command code action 94h write block 95h read block 96h reboot eeprom in register file 97h trigger fault store to eeprom 98h extended page access on 99h extended page access off 9ah eeprom page access on 9bh eeprom page access off 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 47
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 48 ______________________________________________________________________________________ 8) the slave asserts an ack on sda. 9) the slave sends the 8-bit byte count (16). 10) the master asserts an ack on sda. 11) the slave sends 8 bits of data. 12) the master asserts an ack on sda. 13) repeat steps 11 and 12 up to fifteen times. 14) the master asserts a nack on sda. 15) the master sends a stop condition. read byte format s slave address slave address ack command ack sr ack data byte nack p 7 bits 8 bits 7 bits 8 bits command byte: prepares device for following read. data byte: data comes from the register set by the command byte. 01 block write format s address ack command ack byte count= n ack data byte 1 ack data byte ... ack data byte n ack p 7 bits 8 bits 8 bits 8 bits 8 bits command byte: destination address data byte: data goes into the register set by the command 8 bits 0 block read format s address ack command ack sr address ack byte count= n ack ack ack nack p 7 bits 8 bits 7 bits 8 bits 8 bits 8 bits 8 bits command byte: prepares device for block operation. data byte: data is read from the register (or eeprom location) set by the command code 0 1 slave to master master to slave s address 7 bits send byte format wr ack data 8 bits ack p data byte: presets the internal address pointer or represents a command. slave address: equivalent to chip- select line of a 3-wire interface. slave address: equivalent to chip- select line of a 3-wire interface. slave address: equivalent to chip- select line of a 3-wire interface. slave address: equivalent to chip- select line of a 3-wire interface. slave address: equivalent to chip- select line of a 3-wire interface. slave address: equivalent to chip- select line of a 3-wire interface. slave address: equivalent to chip- select line of a 3-wire interface. data byte: presets the internal address pointer or represents a command. slave address: equivalent to chip- select line of a 3-wire interface. 0 write byte format s address ack command ack data ack p 7 bits 8 bits 8 bits command byte: selects register or eeprom location you are writing to. data byte: data goes into the register (or eeprom location) set by the command byte. 0 s = start condition p = stop condition sr = repeated start condition d.c. = don't care ack = acknowledge, sda pulled low during rising edge of scl nack = not acknowlege, sda left high during rising edge of scl all data is clocked in/out of the device on rising edges of scl = sda transistions from high to low during period of scl = sda transistions from low to high during period of scl s address 7 bits receive byte format wr wr wr wr wr wr wr ack data 8 bits nack p 1 data byte 1 data byte ... data byte n figure 12: i 2 c/smbus protocols
max16047/max16049 jtag serial interface the max16047/max16049 contain a jtag port that complies with a subset of the ieee 1149.1 specifica- tion. either the i 2 c or the jtag interface may be used to access internal memory; however, only one interface is allowed to run at a time. the max16047/max16049 do not support ieee 1149.1 boundary-scan functionali- ty. the max16047/max16049 contain extra jtag instructions and registers not included in the jtag specification that provide access to internal memory. the extra instructions include load address, write data, read data, reboot, save, and usercode. test access port (tap) controller instruction register [length = 5 bits] bypass register [length = 1 bit] identification register [length = 32 bits] user code register [length = 32 bits] memory address register [length = 8 bits] memory read register [length = 8 bits] memory write register [length = 8 bits] 11111 00000 00011 00100 00101 00110 00111 mux 2 tdo tdi tms tck 01000 registers and eeprom 01001 01010 01011 01100 mux 1 00111 01000 01001 01010 01011 01100 reboot save setextram seteepadd rstextram rsteepadd command decoder r pu v db figure 13. jtag block diagram 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 49 ieee is a registered service mark of the institute of electrical and electronics engineers, inc.
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 50 ______________________________________________________________________________________ test access port (tap) controller state machine the tap controller is a finite state machine that responds to the logic level at tms on the rising edge of tck. see figure 14 for a diagram of the finite state machine. the possible states are described below: test-logic-reset: at power-up, the tap controller is in the test-logic-reset state. the instruction register con- tains the idcode instruction. all system logic of the device operates normally. this state can be reached from any state by driving tms high for five clock cycles. run-test/idle: the run-test/idle state is used between scan operations or during specific tests. the instruction register and test data registers remain idle. select-dr-scan: all test data registers retain their pre- vious state. with tms low, a rising edge of tck moves the controller into the capture-dr state and initiates a scan sequence. tms high during a rising edge on tck moves the controller to the select-ir-scan state. capture-dr: data can be parallel-loaded into the test data registers selected by the current instruction. if the instruction does not call for a parallel load or the select- ed test data register does not allow parallel loads, the test data register remains at its current value. on the rising edge of tck, the controller goes to the shift-dr state if tms is low or it goes to the exit1-dr state if tms is high. test-logic-reset 1 1 11 0 0 run-test/idle 0 0 0 0 1 1 1 0 0 1 0 1 1 0 1 0 1 select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 0 0 0 0 1 1 0 1 1 figure 14. tap controller state diagram
max16047/max16049 shift-dr: the test data register selected by the current instruction connects between tdi and tdo and shifts data one stage toward its serial output on each rising edge of tck while tms is low. on the rising edge of tck, the controller goes to the exit1-dr state if tms is high. exit1-dr: while in this state, a rising edge on tck puts the controller in the update-dr state. a rising edge on tck with tms low puts the controller in the pause-dr state. pause-dr: shifting of the test data registers halts while in this state. all test data registers retain their previous state. the controller remains in this state while tms is low. a rising edge on tck with tms high puts the con- troller in the exit2-dr state. exit2-dr: a rising edge on tck with tms high while in this state puts the controller in the update-dr state. a ris- ing edge on tck with tms low enters the shift-dr state. update-dr: a falling edge on tck while in the update- dr state latches the data from the shift register path of the test data registers into a set of output latches. this prevents changes at the parallel output because of changes in the shift register. on the rising edge of tck, the controller goes to the run-test/idle state if tms is low or goes to the select-dr-scan state if tms is high. select-ir-scan: all test data registers retain their previ- ous states. the instruction register remains unchanged during this state. with tms low, a rising edge on tck moves the controller into the capture-ir state. tms high during a rising edge on tck puts the controller back into the test-logic-reset state. capture-ir: use the capture-ir state to load the shift register in the instruction register with a fixed value. this value is loaded on the rising edge of tck. if tms is high on the rising edge of tck, the controller enters the exit1-ir state. if tms is low on the rising edge of tck, the controller enters the shift-ir state. shift-ir: in this state, the shift register in the instruction register connects between tdi and tdo and shifts data one stage for every rising edge of tck toward the tdo serial output while tms is low. the parallel outputs of the instruction register as well as all test data regis- ters remain at their previous states. a rising edge on tck with tms high moves the controller to the exit1-ir state. a rising edge on tck with tms low keeps the controller in the shift-ir state while moving data one stage through the instruction shift register. exit1-ir: a rising edge on tck with tms low puts the controller in the pause-ir state. if tms is high on the rising edge of tck, the controller enters the update-ir state. pause-ir: shifting of the instruction shift register halts temporarily. with tms high, a rising edge on tck puts the controller in the exit2-ir state. the controller remains in the pause-ir state if tms is low during a ris- ing edge on tck. exit2-ir: a rising edge on tck with tms high puts the controller in the update-ir state. the controller loops back to shift-ir if tms is low during a rising edge of tck in this state. update-ir: the instruction code that has been shifted into the instruction shift register latches to the parallel outputs of the instruction register on the falling edge of tck as the controller enters this state. once latched, this instruction becomes the current instruction. a rising edge on tck with tms low puts the controller in the run-test/idle state. with tms high, the controller enters the select-dr-scan state. instruction register the instruction register contains a shift register as well as a latched parallel output and is 5 bits in length. when the tap controller enters the shift-ir state, the instruc- tion shift register connects between tdi and tdo. while in the shift-ir state, a rising edge on tck with tms low shifts the data one stage toward the serial output at tdo. a rising edge on tck in the exit1-ir state or the exit2-ir state with tms high moves the controller to the update-ir state. the falling edge of that same tck latches the data in the instruction shift register to the instruction register parallel output. instructions support- ed by the max16047/max16049 and the respective operational binary codes are shown in table 27. 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 51
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 52 ______________________________________________________________________________________ bypass: when the bypass instruction is latched into the instruction register, tdi connects to tdo through the 1-bit bypass test data register. this allows data to pass from tdi to tdo without affecting the device? normal operation. idcode: when the idcode instruction is latched into the parallel instruction register, the identification data register is selected. the device identification code is loaded into the identification data register on the rising edge of tck following entry into the capture-dr state. shift-dr can be used to shift the identification code out serially through tdo. during test-logic-reset, the idcode instruction is forced into the instruction regis- ter. the identification code always has a ??in the lsb position. the next 11 bits identify the manufacturer? jedec number and number of continuation bytes fol- lowed by 16 bits for the device and 4 bits for the ver- sion. see table 28. table 27. jtag instruction set instruction hex code selected register/action bypass 1fh bypass. mandatory instruction code. idcode 00h manufacturer id code and part number usercode 03h user code (user-defined id) load address 04h load address register content read data 05h memory read write data 06h memory write reboot 07h resets the device save 08h stores current fault information in eeprom setextram 09h extended page access on rstextram 0ah extended page access off seteepadd 0bh eeprom page access on rsteepadd 0ch eeprom page access off table 28. 32-bit identification code msb lsb version (4 bits) device id (16 bits) manufacturer id (11 bits) fixed value (1 bit) 0000 0000000000000001 00011001011 1 table 29. 32-bit user-code data msb lsb d.c. (don? cares) i 2 c/smbus slave address user identification (firmware version) 00000000000000000 see table 31 r5ch[7:0] contents usercode: when the usercode instruction latches into the parallel instruction register, the user-code data register is selected. the device user-code loads into the user-code data register on the rising edge of tck following entry into the capture-dr state. shift-dr can be used to shift the user-code out serially through tdo. see table 29. this instruction may be used to help identify multiple max16047/max16049 devices con- nected in a jtag chain.
max16047/max16049 load address: this is an extension to the standard ieee 1149.1 instruction set to support access to the memory in the max16047/max16049. when the load address instruction latches into the instruction regis- ter, tdi connects to tdo through the 8-bit memory address test data register during the shift-dr state. read data: this is an extension to the standard ieee 1149.1 instruction set to support access to the memory in the max16047/max16049. when the read data instruction latches into the instruction register, tdi con- nects to tdo through the 8-bit memory read test data register during the shift-dr state. write data: this is an extension to the standard ieee 1149.1 instruction set to support access to the memory in the max16047/max16049. when the write data instruction latches into the instruction register, tdi connects to tdo through the 8-bit memory write test data register during the shift-dr state. reboot: this is an extension to the standard ieee 1149.1 instruction set to initiate a software controlled reset to the max16047/max16049. when the reboot instruction latches into the instruction register, the max16047/max16049 resets and immediately begins the boot-up sequence. save: this is an extension to the standard ieee 1149.1 instruction set that triggers a fault log. the current adc conversion results along with fault information are saved to eeprom depending on the configuration of the critical fault log control register (r47h). setextram : this is an extension to the standard ieee 1149.1 instruction set that allows access to the extend- ed page. extended registers include adc conversion results and gpio input/output data. rstextram: this is an extension to the standard ieee 1149.1 instruction set. use rstextram to return to the default page and disable access to the extended page. seteepadd: this is an extension to the standard ieee 1149.1 instruction set that allows access to the eeprom page. once the seteepadd command has been sent, all addresses are recognized as eeprom addresses only. when accessing any eeprom location, set the address to the desired location, perform a dummy read data operation, and then set the address back to the desired location. this primes the device for a subsequent series of read data operations. rsteepadd: this is an extension to the standard ieee 1149.1 instruction set. use rsteepadd to return to the default page and disable access to the eeprom. applications information unprogrammed device behavior when the eeprom has not been programmed using the jtag or i 2 c interface, the default configuration of the en_out_ outputs is open-drain active-low. if it is neces- sary to hold an en_out_ high or low to prevent prema- ture startup of a power supply before the eeprom is programmed, connect a resistor to ground or the supply voltage. avoid connecting a resistor to ground if the out- put is to be configured as open-drain with a separate pullup resistor. device behavior at power-up when v cc is ramped from 0v, the reset output is high impedance until v cc reaches 1.4v, at which point it is driven low. all other outputs are high impedance until v cc reaches 2.85v, when the eeprom contents are copied into register memory, and after which the out- puts assume their programmed states. maintaining power during a fault condition power to the max16047/max16049 must be main- tained for a specific period of time to ensure a success- ful eeprom fault log operation during a fault that removes power to the circuit. the amount of time required depends on the settings in the fault control register (r47h[1:0]) according to table 30. table 30. eeprom fault log operation period fault control register value r47h[1:0] description required period t fault _ save (ms) 00 failed lines and adc values saved 204 01 failed lines saved 60 10 adc values saved 168 11 no information saved 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 53
maintain power for shutdown during fault conditions in applications where the always-on power supply cannot be relied upon by placing a diode and a large capaci- tor between the voltage source, v in , and v cc (figure 15). the capacitor value depends on v in and the time delay required, t fault_save . use the following formula to calculate the capacitor size: where the capacitance is in farads and t fault_save is in seconds. i cc(max) is 5ma, v diode is the voltage drop across the diode, and v uvlo is 2.85v. for exam- ple, with a v in of 14v, a diode drop of 0.7v, and a t fault_save of 0.204s, the minimum required capaci- tance is 100?. driving high-side mosfet switches the max16047/max16049 use external n-channel mosfet switches for voltage tracking applications. to configure the part for closed-loop voltage tracking using series-pass mosfets, configure up to four of the pro- grammable outputs (en_out1?n_out4) of the max16047/max16049 as closed-loop tracking outputs and configure up to four of the gpios as sense-return inputs (ins1?ns4). connect the en_out_ output to the gate of an n-channel mosfet, connect the source of the mosfet to the ins_ feedback input, and monitor the drain side of the mosfet with the corresponding mon_ input (see figure 16). both the input and the output must be assigned to the same slot (see the closed?oop tracking section). configure the power-up and power- down slew rates in the configuration registers. to provide additional control over power-down, enable the internal 100 pulldown resistors on the ins_ connections. up to six of the programmable outputs (en_out1 en_out6) of the max16047/max16049 may be config- ured as charge-pump outputs. in this case, they can drive the gates of series-pass n-channel mosfets with- out closed-loop tracking functionality. when configured in this way, these outputs act as simple power switches to turn on the voltage supply rails. approximate the slew rate, sr, using the following formula: where i cp is the 6? (typ) charge-pump source cur- rent, c gate is the gate capacitance of the mosfet, and c ext is the capacitance connected from the gate to ground. power-down is not well controlled due to the absence of the 100 pulldowns. if more than six series-pass mosfets are required for an application, additional series-pass p-channel mosfets may be connected to outputs configured as active-low open drain (figure 17). connect a pullup resistor from the gate to the source of the mosfet, and ensure the absolute maximum ratings of the max16047/max16049 are not exceeded. sr i cc cp gate ext = + () c ti vv v fault_save cc(max) in diode cc(min) = ? ? max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 54 ______________________________________________________________________________________ max16047/max16049 max16047 max16049 v cc c v in gnd figure 15. power circuit for shutdown during fault conditions mon_ en_out_ ins_ v in v out reference ramp logic adc mux v th_pg 100 gate drive figure 16. closed-loop tracking
max16047/max16049 table 31. recommended mosfets manufacturer part max v ds (v) v gs _ th (v) r ds(on) at v gs = 4.5v (m ) i max at 50mv voltage drop (a) q g (typ) (nc) package fdc633n 30 0.67 42 1.19 11 super sot-6 fdp8030l fdb8030l 30 1.5 4.5 11.11 120 to-220 to-263ab fdd6672a 30 1.2 9.5 5.26 33 to-252 fairchild fds8876 30 2.5 10.2 2.94 15 so-8 si7136dp 20 3 4.5 11.11 24.5 so-8 si4872dy 30 1 10 5 27 so-8 sud50n02-09p 20 3 17 2.94 10.5 to-252 vishay si1488dh 20 0.95 49 1.02 6 sot-363 sc70-6 irl3716 20 3 4.8 10.4 53 to220ab d 2 pak to-262 irl3402 20 0.7 10 5 78 (max) to220ab irl3715z 20 2.1 15.5 3.22 7 to220ab d 2 pak to-262 international rectifier irlm2502 20 1.2 45 1.11 8 sot23-3 micro3 simple slew-rate control is accomplished by adding a capacitor from the gate to ground. the slew rate is approximated by the rc charge curve of the pullup resistor acting with the capacitor from gate to ground. note that the power-off is not well controlled due to the absence of the 100 pulldowns. ensure that mosfets have a low gate-to-source threshold (v gs_th ) and r ds(on) . see table 31 for rec- ommended n-channel mosfets. layout and bypassing bypass dbp and abp each with a 1? ceramic capacitor to gnd. bypass v cc with a 10? capacitor to ground. avoid routing digital return currents through a sensitive analog area, such as an analog supply input return path or abp? bypass capacitor ground connection. use dedi- cated analog and digital ground planes. connect the capacitors as close as possible to the device. 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 55 max16047 max16049 v out d s g r mon_ en_out_ v in figure 17. connection for a p-channel series-pass mosfet
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 56 ______________________________________________________________________________________ register map page address read/write description ext 00h r mon1 adc result register (msb) ext 01h r mon1 adc result register (lsb) ext 02h r mon2 adc result register (msb) ext 03h r mon2 adc result register (lsb) ext 04h r mon3 adc result register (msb) ext 05h r mon3 adc result register (lsb) ext 06h r mon4 adc result register (msb) ext 07h r mon4 adc result register (lsb) ext 08h r mon5 adc result register (msb) ext 09h r mon5 adc result register (lsb) ext 0ah r mon6 adc result register (msb) ext 0bh r mon6 adc result register (lsb) ext 0ch r mon7 adc result register (msb) ext 0dh r mon7 adc result register (lsb) ext 0eh r mon8 adc result register (msb) ext 0fh r mon8 adc result register (lsb) ext 10h r mon9 adc result register (msb)* ext 11h r mon9 adc result register (lsb)* ext 12h r mon10 adc result register (msb)* ext 13h r mon10 adc result register (lsb)* ext 14h r mon11 adc result register (msb)* ext 15h r mon11 adc result register (lsb)* ext 16h r mon12 adc result register (msb)* ext 17h r mon12 adc result register (lsb)* ext 18h r/w fault register?ailed line flags ext 19h r/w fault register?ailed line flags ext 1ah r/w gpio data out ext 1bh r gpio data in ext 1ch?dh r/w reserved default 00h?bh r/w reserved eeprom 00h r/w power-up fault registers eeprom 01h r/w failed line flags (fault registers) eeprom 02h r/w failed line flags (fault registers) eeprom 03h r/w mon1 conversion result at time of fault eeprom 04h r/w mon2 conversion result at time of fault eeprom 05h r/w mon3 conversion result at time of fault eeprom 06h r/w mon4 conversion result at time of fault eeprom 07h r/w mon5 conversion result at time of fault eeprom 08h r/w mon6 conversion result at time of fault eeprom 09h r/w mon7 conversion result at time of fault
max16047/max16049 register map (continued) page address read/write description eeprom 0ah r/w mon8 conversion result at time of fault eeprom 0bh r/w mon9 conversion result at time of fault* eeprom 0ch r/w mon10 conversion result at time of fault* eeprom 0dh r/w mon11 conversion result at time of fault* eeprom 0eh r/w mon12 conversion result at time of fault* def/ee 0fh r/w adc mon4?on1 voltage ranges def/ee 10h r/w adc mon8?on5 voltage ranges def/ee 11h r/w adc mon12?on9 voltage ranges* def/ee 12h?4h r/w reserved def/ee 15h r/w fault1 dependencies def/ee 16h r/w fault1 dependencies def/ee 17h r/w fault2 dependencies def/ee 18h r/w fault2 dependencies def/ee 19h r/w reset output configuration def/ee 1ah r/w reset output dependencies def/ee 1bh r/w reset output dependencies def/ee 1ch r/w gpio configuration def/ee 1dh r/w gpio configuration def/ee 1eh r/w gpio configuration def/ee 1fh r/w en_out1?n_out3 output configuration def/ee 20h r/w en_out3?n_out6 output configuration def/ee 21h r/w en_out6?n_out9 output configuration* def/ee 22h r/w en_out10?n_out12 output configuration* def/ee 23h r/w mon1 early warning threshold def/ee 24h r/w mon1 overvoltage threshold def/ee 25h r/w mon1 undervoltage threshold def/ee 26h r/w mon2 early warning threshold def/ee 27h r/w mon2 overvoltage threshold def/ee 28h r/w mon2 undervoltage threshold def/ee 29h r/w mon3 early warning threshold def/ee 2ah r/w mon3 overvoltage threshold def/ee 2bh r/w mon3 undervoltage threshold def/ee 2ch r/w mon4 early warning threshold def/ee 2dh r/w mon4 overvoltage threshold def/ee 2eh r/w mon4 undervoltage threshold def/ee 2fh r/w mon5 early warning threshold def/ee 30h r/w mon5 overvoltage threshold def/ee 31h r/w mon5 undervoltage threshold def/ee 32h r/w mon6 early warning threshold def/ee 33h r/w mon6 overvoltage threshold 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 57
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 58 ______________________________________________________________________________________ register map (continued) page address read/write description def/ee 34h r/w mon6 undervoltage threshold def/ee 35h r/w mon7 early warning threshold def/ee 36h r/w mon7 overvoltage threshold def/ee 37h r/w mon7 undervoltage threshold def/ee 38h r/w mon8 early warning threshold def/ee 39h r/w mon8 overvoltage threshold def/ee 3ah r/w mon8 undervoltage threshold def/ee 3bh r/w mon9 early warning threshold* def/ee 3ch r/w mon9 overvoltage threshold* def/ee 3dh r/w mon9 undervoltage threshold* def/ee 3eh r/w mon10 early warning threshold* def/ee 3fh r/w mon10 overvoltage threshold* def/ee 40h r/w mon10 undervoltage threshold* def/ee 41h r/w mon11 early warning threshold* def/ee 42h r/w mon11 overvoltage threshold* def/ee 43h r/w mon11 undervoltage threshold* def/ee 44h r/w mon12 early warning threshold* def/ee 45h r/w mon12 overvoltage threshold* def/ee 46h r/w mon12 undervoltage threshold* def/ee 47h r/w fault control def/ee 48h r/w faults causing emergency eeprom save def/ee 49h r/w faults causing emergency eeprom save def/ee 4ah r/w faults causing emergency eeprom save def/ee 4bh r/w faults causing emergency eeprom save def/ee 4ch r/w faults causing emergency eeprom save def/ee 4dh r/w software enable /margin def/ee 4eh r/w power-up/power-down pulldown resistors def/ee 4fh r/w autoretry, slew rate, and adc fault deglitch def/ee 50h r/w sequence delays def/ee 51h r/w sequence delays def/ee 52h r/w sequence delays def/ee 53h r/w sequence delays def/ee 54h r/w sequence delays/reverse-sequence bit def/ee 55h r/w watchdog timer setup def/ee 56h r/w mon2?on1 slot assignment from slot 1 to slot 12 def/ee 57h r/w mon4?on3 slot assignment from slot 1 to slot 12 def/ee 58h r/w mon6?on5 slot assignment from slot 1 to slot 12 def/ee 59h r/w mon8?on7 slot assignment from slot 1 to slot 12 def/ee 5ah r/w mon10?on9 slot assignment from slot 1 to slot 12*
max16047/max16049 max16047/max16049 register map (continued) page address read/write description def/ee 5bh r/w mon12?on11 slot assignment from slot 1 to slot 12* def/ee 5ch r/w customer firmware version def/ee 5dh r/w eeprom and configuration lock def/ee 5eh r/w en_out2?n_out1 slot assignment from slot 0 to slot 11 def/ee 5fh r/w en_out4?n_out2 slot assignment from slot 0 to slot 11 def/ee 60h r/w en_out6?n_out5 slot assignment from slot 0 to slot 11 def/ee 61h r/w en_out8?n_out7 slot assignment from slot 0 to slot 11 def/ee 62h r/w en_out10?n_out9 slot assignment from slot 0 to slot 11* def/ee 63h r/w en_out12?n_out11 slot assignment from slot 0 to slot 11* def/ee 64h r/w ins power-good (pg) thresholds def/ee 65h r manufacturing revision code def/ee 66h?3h reserved eeprom 9ch?fh r/w user eeprom selector guide part voltage detector inputs general-purpose inputs/outputs sequencing outputs MAX16047ETN+ 12 6 12 max16049etn+ 868 * max16047 only note: ext refers to registers contained in the extended page, default refers to registers contained in the default page, eeprom refers to eeprom memory locations, and def/ee refers to locations that are stored in eeprom and loaded into the same addresses in the default page on boot-up. chip information process: bicmos 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 59 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package draw- ings may show a different suffix character, but the drawing per- tains to the package regardless of rohs status. package type package code outline no. land pattern no. 56 tqfn-ep t5688+3 21-0135 90-0047
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 60 ______________________________________________________________________________________ max16047/max16049 pin configurations 46 47 48 49 50 43 44 45 51 29 30 31 32 33 34 35 36 37 38 mon11 sda en_out7 tqfn (8mm x 8mm) + top view en_out6 en_out5 en_out4 en_out3 en_out2 en_out1 gpio4 gpio3 scl tdi tms tdo tck gpio6 gnd en gpio5 n.c. n.c. n.c. n.c. mon10 mon9 mon8 mon7 mon6 a0 reset mon12 mon5 mon4 mon3 mon2 39 mon1 n.c. n.c. n.c. n.c. n.c. abp n.c. ep n.c. n.c. v cc dbp gnd gpio1 gpio2 52 en_out8 53 54 55 en_out11 en_out10 en_out9 56 en_out12 20 19 18 17 16 24 23 22 21 15 26 25 28 27 40 41 42 11 10 9 8 7 6 5 4 3 2 14 13 12 1 max16047 46 47 48 49 50 43 44 45 51 29 30 31 32 33 34 35 36 37 38 n.c. sda en_out7 tqfn (8mm x 8mm) + en_out6 en_out5 en_out4 en_out3 en_out2 en_out1 gpio4 gpio3 scl tdi tms tdo tck gpio6 gnd en gpio5 n.c. n.c. n.c. n.c. n.c. n.c. mon8 mon7 mon6 a0 reset n.c. mon5 mon4 mon3 mon2 39 mon1 n.c. n.c. n.c. n.c. n.c. abp n.c. ep n.c. n.c. v cc dbp gnd gpio1 gpio2 52 en_out8 53 54 55 n.c. n.c. n.c. 56 n.c. 20 19 18 17 16 24 23 22 21 15 26 25 28 27 40 41 42 11 10 9 8 7 6 5 4 3 2 14 13 12 1 max16049
max16047/max16049 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers revision history revision number revision date description pages changed 0 11/07 initial release 1 2/08 removed future product designation in the ordering information table and updated package information . 1, 61, 62 2 12/08 updated the register summary (all registers 8-bits wide) section. 14 3 3/09 updated detailed description , table 24, and table 25. 15, 27, 28, 34, 38, 39, 43, 45 4 9/10 revised the electrical characteristics and instruction register section. 5, 53 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 61 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc.

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